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51.发明申请公开(公告)号：US20140145696A1
公开(公告)日：2014-05-29
申请号：US14130688
申请日：2012-07-03
申请人： Kenichi Hoshino , Teppei Hirotsu , Ryosuke Ishida
发明人： Kenichi Hoshino , Teppei Hirotsu , Ryosuke Ishida
IPC分类号： H02M3/157
CPC分类号： H02M3/157 , F02D2041/2024 , F02D2041/2058 , H03M1/0609 , H03M1/12
摘要： A current control semiconductor device that can detect a current with high precision within an IC of one chip by dynamically correcting a variation in a gain a and an offset b, and a control device using the semiconductor device are provided. A transistor 4, a current-voltage converter circuit 22, and an AD converter 23 are disposed on an identical semiconductor chip. Reference current generator circuits 6 and 6′ superimpose a current pulse Ic on a current of a load 2, and vary a voltage digital value output by the AD converter. A gain/offset correction unit 8 subjects a variation in a voltage digital value caused by the reference current generator circuits 6, 6′ to signal processing, and dynamically acquires gains a, a′ and offsets b, b′ in a linear relational expression of the voltage digital value output by the AD converter 23 and a current digital value of the load. A current digital value calculation unit 12 corrects a voltage value output by the AD converter with the use of the gain and the offset acquired by the gain/offset correction unit 8.
摘要翻译： 提供了一种电流控制半导体器件，其通过动态地校正增益a和偏移b的变化，以及使用该半导体器件的控制装置，能够以一个芯片的IC内的高精度检测电流。 晶体管4，电流 - 电压转换器电路22和AD转换器23设置在相同的半导体芯片上。 参考电流发生器电路6和6'将电流脉冲Ic叠加在负载2的电流上，并且改变由AD转换器输出的电压数字值。 增益/偏移校正单元8使由参考电流发生器电路6,6'引起的电压数字值的变化进行信号处理，并且以线性关系表达式动态地获取增益a，a'和偏移量b，b' 由AD转换器23输出的电压数字值和负载的当前数字值。 当前数字值计算单元12利用由增益/偏移校正单元8获取的增益和偏移来校正由AD转换器输出的电压值。
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公开(公告)号：US20090021406A1
公开(公告)日：2009-01-22
申请号：US12157452
申请日：2008-06-09
CPC分类号： H03M1/0609 , H03M1/0602 , H03M1/1215
摘要： A method and apparatus for compensating for gain offset, bias offset, and skew in a parallel processing environment is disclosed. The method and apparatus may be configured to compensate for mismatches between the sub-channel signals in a parallel ADC. This allows for accurate combination of the signals on the sub-channels. The method and apparatus may be utilized in a high speed data communication system having two or more channels, each of which are interleaved into two or more sub-channels. In one embodiment a DC loop processes signals on two or more sub-channels to account for and remove unwanted bias offset. In one embodiment a sub-channel gain mismatch compensation system (SCGMC) processes signals on two or more sub-channels to account for and remove unwanted gain offset. In one embodiment a skew compensation system, such as a parallel interpolator, processes signals on two or more sub-channels to remove unwanted skew across sub-channels.
摘要翻译： 公开了一种用于在并行处理环境中补偿增益偏移，偏移偏移和偏斜的方法和装置。 该方法和装置可以被配置为补偿并行ADC中的子信道信号之间的失配。 这允许子通道上的信号的精确组合。 该方法和装置可以用于具有两个或更多个信道的高速数据通信系统，每个信道被交织成两个或更多个子信道。 在一个实施例中，DC环路在两个或更多个子信道上处理信号以考虑和去除不想要的偏移偏移。 在一个实施例中，子信道增益失配补偿系统（SCGMC）处理两个或更多个子信道上的信号以考虑和去除不期望的增益偏移。 在一个实施例中，诸如并行内插器的偏斜补偿系统处理两个或更多个子通道上的信号以去除跨子通道的不期望的偏斜。
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53.发明授权公开(公告)号：US07450044B2
公开(公告)日：2008-11-11
申请号：US11692128
申请日：2007-03-27
申请人： George S. Moore , Nico Lugil , Kenneth D. Poulton
发明人： George S. Moore , Nico Lugil , Kenneth D. Poulton
IPC分类号： H03M1/06
CPC分类号： H03M1/0609 , H03M1/0624 , H03M1/1028 , H03M1/1042 , H03M1/662
摘要： A digital-to-analog conversion system comprises a digital input, a digital-to-analog converter and a modified digital signal generator. The digital-to-analog converter has a conversion frequency and is subject to a periodic error having a periodicity equal to that of an N-th sub-harmonic of the conversion frequency, where N is an integer. The digital input is operable to receive a digital input signal. The modified digital signal generator is interposed between the digital input and the digital-to-analog converter and is operable in response to the digital input signal to generate a modified digital signal. The modified digital signal comprises a dynamic digital mitigation component that mitigates the periodic error of the digital-to-analog converter.
摘要翻译： 数模转换系统包括数字输入，数模转换器和经修改的数字信号发生器。 数模转换器具有转换频率，并且经受周期性误差，其周期性等于转换频率的第N次谐波的周期性，其中N是整数。 数字输入可操作以接收数字输入信号。 经修改的数字信号发生器插入在数字输入和数模转换器之间，并且响应于数字输入信号可操作以产生经修改的数字信号。 经修改的数字信号包括减轻数 - 模转换器的周期性误差的动态数字缓解部件。
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54.发明公开公开(公告)号：US20240187012A1
公开(公告)日：2024-06-06
申请号：US18553212
申请日：2021-06-25
申请人： Intel Corporation
CPC分类号： H03M1/0609 , H03M1/1042 , H03M1/188
摘要： An analog-to-digital converter (ADC) system is provided. The ADC system includes a first signal path. The first signal path includes a first ADC configured to generate first digital data based on an input signal. The first ADC is a time-interleaved ADC including a plurality of sub-ADCs. The first signal path further includes circuitry configured to output activity data indicating at least which of the plurality of sub-ADCs is currently active. The ADC system further includes a correction circuit configured to output digital correction data based on the activity data. Further, the ADC system includes a second signal path coupled in parallel to the first signal path. The second signal path includes a second ADC configured to generate second digital data based on the input signal and a combiner circuit configured to generate modified second digital data by combining the second digital data and the correction data. The ADC system further includes an equalizer configured to generate an equalized output signal of the ADC system based on the first digital data. The equalizer is configured to adjust, based on the modified second digital data, at least one equalization parameter used for generating the equalized output signal of the ADC system.
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55.发明公开公开(公告)号：US20240072817A1
公开(公告)日：2024-02-29
申请号：US17899149
申请日：2022-08-30
发明人： Prasanth K , Rahul Sharma
CPC分类号： H03M1/0609 , H03M1/1023
摘要： An example analog-to-digital converter (ADC) comprising: sample and hold circuitry coupled to an analog input; a first sub-ADC coupled to the sample and hold circuitry; a multiplying digital-to-analog converter (M-DAC) coupled to the first sub-ADC; summation circuitry coupled to the sample and hold circuitry and the M-DAC; an amplifier coupled to the summation circuitry; a second sub-ADC coupled to the amplifier; and reference generation circuitry coupled to the first sub-ADC, the M-DAC, and the second sub-ADC, the reference generation circuitry including: reference voltage circuitry coupled to the M-DAC; a first resistor coupled to the reference voltage circuitry; a second resistor coupled to the first resistor; and a capacitor coupled in parallel to the second resistor by a switch.
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公开(公告)号：US20170310334A1
公开(公告)日：2017-10-26
申请号：US15507704
申请日：2015-09-02
发明人： Shuo-Wei Chen
CPC分类号： H03M1/1245 , H03M1/0609 , H03M1/10 , H03M1/14 , H03M1/502 , H03M1/60
摘要： An analog-to-digital converter may convert an analog signal into digital codes representative of the changing level of the analog signal. An analog high pass filter may receive and continuously differentiate the analog signal. A voltage controlled oscillator may receive the differentiated analog signal and continuously generates an output that is an integral of the differentiated analog signal in the phase domain. A time-to-digital converter may sample the output of the voltage controlled oscillator and convert each sample into a digital code representative of the current phase of the sampled output of the voltage controlled oscillator.
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公开(公告)号：US09742420B2
公开(公告)日：2017-08-22
申请号：US14954577
申请日：2015-11-30
发明人： Sriram Narayanan , Srinath Ramaswamy , Arup Polley , Ajit Sharma
CPC分类号： H03M1/0609 , H03M1/001 , H03M1/002 , H03M1/1295 , H03M1/162
摘要： An analog to digital converter (ADC) system that includes a first amplifier configured to amplify an analog input signal to produce an amplified direct current (DC) signal, an ADC configured to receive the amplified DC signal and convert the amplified DC signal into a digital DC signal, a digital to analog converter configured to receive the digital DC signal and convert the digital DC signal into an analog DC signal, and a second amplifier configured to receive an analog alternating current (AC) signal comprising the analog DC signal subtracted from the analog input signal and amplify the analog AC signal to produce an amplified AC signal. The ADC is further configured to receive the amplified AC signal and produce a digital AC signal. The second amplifier has a gain greater than a gain of the first amplifier.
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公开(公告)号：US09716945B2
公开(公告)日：2017-07-25
申请号：US14787052
申请日：2014-04-23
IPC分类号： H04R19/00 , H04R3/06 , G01D5/244 , G01P15/125 , G01D5/24 , H03M1/06 , H03M3/00 , H04R19/04 , H04R29/00 , G01P15/08 , G01D3/02 , H03M1/12
CPC分类号： H04R3/06 , G01D3/02 , G01D5/24 , G01D5/24476 , G01P15/125 , G01P2015/0865 , H03M1/0609 , H03M1/12 , H03M3/352 , H03M3/458 , H04R19/005 , H04R19/04 , H04R29/004 , H04R2201/003 , H04R2499/11
摘要： This application relates to circuitry for processing sense signals generated by MEMS capacitive transducers for compensating for distortion in such sense signals. The circuitry has a signal path between an input (204) for receiving the sense signal and an output (205) for outputting an output signal based on said sense signal. Compensation circuitry (206, 207) is configured to monitor the signal at a first point along the signal path and generate a correction signal (Scorr); and modify the signal at at least a second point along said signal path based on said correction signal. The correction signal is generated as a function of the value of the signal at the first point along the signal path so as to introduce compensation components into the output signal that compensate for distortion components in the sense signal. The first point in the signal path may be before or after the second point in the signal path. The monitoring may be performed in an analogue or a digital part of the signal path and in either case the modification may be applied in an analogue or a digital part of the signal path.
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59.发明授权公开(公告)号：US09641186B2
公开(公告)日：2017-05-02
申请号：US14732700
申请日：2015-06-06
发明人： Axel Thomsen , Alan L. Westwick
CPC分类号： H03M1/0607 , H03K5/003 , H03M1/00 , H03M1/002 , H03M1/0609 , H03M1/66 , H03M1/664 , H03M1/682 , H03M1/747 , H03M1/808
摘要： Apparatus and associated methods are disclosed for digital-to-analog conversion with improved performance. In one exemplary embodiment, an apparatus includes a DAC to convert a digital input signal to an analog output signal. The DAC includes a decoder to decode the digital input signal and to provide first and second sets of control signals. The DAC also includes a resistor DAC (RDAC) to provide first and second voltages in response to the first set of control signals. The DAC further includes an interpolator coupled to receive the first and second voltages and to provide a first analog signal in response to the second set of control signals.
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公开(公告)号：US09626335B2
公开(公告)日：2017-04-18
申请号：US13744106
申请日：2013-01-17
发明人： Mark L. Muldowney , Gary Wilks , Yang Wang
CPC分类号： G06F17/00 , H03M1/0609 , H03M1/10 , H03M1/12 , H03M1/1265
摘要： A method of analog to digital conversion for a field device having an analog to digital converter system (ADCS) including an ADC and a plurality of filters. An analog sensing signal is received from a sensor which measures a level of a physical parameter in a manufacturing system that runs a physical process. A level of the physical parameter is compared to reference noise data. Based on the comparing, at least one ADCS parameter is determined. The ADCS parameter is implemented to configure the ADCS. The ADCS is utilized with the ADCS parameter to generate a filtered digitized sensing signal from the analog sensing signal.
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