公开(公告)号：US5121035A

公开(公告)日：1992-06-09

申请号：US661760

申请日：1991-02-27

Applicant: Robert C. Kezer ,  Kenneth R. Elliott

Inventor： Robert C. Kezer ,  Kenneth R. Elliott

IPC: H03K3/356

CPC classification number: H03K3/356026 ,  H03K3/356069

Abstract: A non-inverting gallium arsenide depletion mode latch circuit is responsive to high and low input data, and to clock pulses from a clock having high and low pulses for loading data and for translating data from the input to the output in a single gate delay. The circuit includes a pair of pull-up FETs having their conduction paths connected in parallel with an output node in circuit with the FETs for output data. A positive feedback path is enabled from one of the FETs for reinforcing the data at the output node. The one FET enables the feedback path during clock pulses in the low direction, while the other FET applies data to the node during high clock pulses. Data input FETs enable and disable the other FET in accordance with the input data and selective clock pulses, while a clock pulse input FET enables and disables the one FET in accordance with the clock pulses.

Abstract translation: 非反相砷化镓耗尽型锁存电路对高输入数据和低输入数据进行响应，并对来自具有高和低脉冲的时钟脉冲进行时钟脉冲以加载数据，以及在单个门延迟中将数据从输入转换为输出。 电路包括一对上拉FET，其导通路径与电路中的输出节点并联连接，用于输出数据。 从一个FET启用正反馈路径，用于加强输出节点处的数据。 一个FET在低方向的时钟脉冲期间启用反馈路径，而另一个FET在高时钟脉冲期间将数据应用于节点。 数据输入FET根据输入数据和选择性时钟脉冲启用和禁用另一个FET，而时钟脉冲输入FET根据时钟脉冲启用和禁用一个FET。

公开(公告)号：US5032741A

公开(公告)日：1991-07-16

申请号：US532723

申请日：1990-06-04

Applicant: Robert T. Smith

Inventor： Robert T. Smith

IPC: H03K3/356

CPC classification number: H03K3/356043 ,  H03K3/356026

Abstract: A CDCFL latch circuit having a plurality of inputs and first and second outputs includes a gate circuit responsive to logic input signals supplied to the plurality of inputs for providing complementary output logic signals at the first and second outputs when the gate circuit is rendered operative. A regeneration circuit is coupled to the first and second outputs for maintaining the complementary output logic signals at the first and second outputs when the regeneration circuit is rendered operative and the gate circuit is rendered non-operative. A shared load circuit provides current to the gate circuit when the gate circuit is operative and for providing current to the regeneration circuit when the regeneration circuit is operative. A control circuit responsive to a complementary clock signal and coupled between the shared load circuit and the gate and regeneration circuits alternately renders the gate circuit operative when the complementary clock signal is in a first logic state and the regeneration circuit operative when the complementary clock signal is in a second logic state.

Abstract translation: 具有多个输入和第一和第二输出的CDCFL锁存电路包括响应于提供给多个输入的逻辑输入信号的门电路，用于当门电路工作时在第一和第二输出处提供互补的输出逻辑信号。 再生电路耦合到第一和第二输出端，用于当再生电路工作并使门电路变得无效时，将互补输出逻辑信号保持在第一和第二输出。 当门电路工作时，共享负载电路向门电路提供电流，并且当再生电路工作时，向再生电路提供电流。 当互补时钟信号处于第一逻辑状态时，响应于互补时钟信号并且耦合在共享负载电路和门和再生电路之间的控制电路交替地使门电路工作，并且当互补时钟信号为 处于第二逻辑状态。

公开(公告)号：US4442365A

公开(公告)日：1984-04-10

申请号：US326925

申请日：1981-12-02

Applicant: Akira Nagami

Inventor： Akira Nagami

IPC: G11C11/408 ,  H03K3/356 ,  H03K19/0185 ,  H03K19/096

CPC classification number: H03K3/356026 ,  H03K3/356078

Abstract: A latch circuit has first to fourth nodes. The first node is supplied with a logic signal and the second node is charged at a first potential. A potential at the third node is discharged to the second potential. The fourth node is charged to the first potential. This all happens during a first period, after which, and during a second period, a potential at the second node is transferred to the third node. An inverter transistor is responsive to a level of the logic signal at the first node for discharging a potential of the second node to a second potential when the logic signal level is in the first potential and for retaining the first potential of the second node when the logic signal level is in the second potential. A transfer between the fourth and the first nodes is responsive to the second potential at the third node for discharging the potential of the fourth node to the second potential. A true and a complement signals of a large amplitude are established at the fourth and second nodes.

Abstract translation: 锁存电路具有第一至第四节点。 第一个节点被提供一个逻辑信号，第二个节点以第一个电位充电。 第三节点处的电位被放电到第二个电位。 第四个节点被充电到第一个电位。 这全部发生在第一时段期间，之后，在第二时段期间，第二节点处的电位被传送到第三节点。 当逻辑信号电平处于第一电位时，逆变器晶体管响应于第一节点处的逻辑信号的电平，用于将第二节点的电位放电到第二电位，并且当第二节点的第一电位保持在第一电位时， 逻辑信号电平处于第二电位。 第四节点和第一节点之间的传输响应于第三节点处的第二电位，用于将第四节点的电位释放到第二电位。 在第四和第二节点处建立大幅度的真实和补码信号。

公开(公告)号：US4375600A

公开(公告)日：1983-03-01

申请号：US260557

申请日：1981-05-05

Applicant: Philip T. Wu

Inventor： Philip T. Wu

IPC: G11C11/41 ,  G11C11/34 ,  G11C11/409 ,  G11C11/4091 ,  H03K3/356 ,  H03K5/02 ,  G11C7/06 ,  G01R19/165 ,  H03K5/08 ,  H03K5/24

CPC classification number: H03K5/023 ,  G11C11/34 ,  G11C11/4091 ,  H03K3/356026 ,  H03K3/356052

Abstract: A memory-array sense amplifier includes a grounded-gate depletion-mode FET connected between a bit line and a sense node. Another FET connects a supply voltage VDD to the sense node when turned on by a clock phase signal. Further FETs form a latch circuit.

Abstract translation: 存储器阵列读出放大器包括连接在位线和感测节点之间的接地栅耗尽型FET。 另一个FET通过时钟相位信号将电源电压VDD连接到感测节点。 另外的FET形成锁存电路。

公开(公告)号：US4291246A

公开(公告)日：1981-09-22

申请号：US17524

申请日：1979-03-05

Applicant: William L. Martino, Jr. ,  Jerry D. Moench

Inventor： William L. Martino, Jr. ,  Jerry D. Moench

IPC: H03K3/356 ,  H03K5/01 ,  G11C8/00 ,  H03K17/30

CPC classification number: H03K3/356026

Abstract: A balanced differential circuit is provided which is useful as an address buffer in digital memories. The circuit is illustrated as a single ended input circuit having complementary outputs. Capacitors are used to couple imbalancing signals into the circuit. Through selective timing of load devices within the circuit power dissipation is kept to a minimum.

Abstract translation: 提供了一种平衡差分电路，可用作数字存储器中的地址缓冲器。 该电路被示为具有互补输出的单端输入电路。 电容器用于将不平衡信号耦合到电路中。 通过电路内的负载设备的选择性定时功耗最小化。

公开(公告)号：US4028558A

公开(公告)日：1977-06-07

申请号：US698622

申请日：1976-06-21

Applicant: Lawrence Griffith Heller ,  Lewis Madison Terman ,  Yen Sung Yee

Inventor： Lawrence Griffith Heller ,  Lewis Madison Terman ,  Yen Sung Yee

IPC: G01R19/165 ,  H03K3/353 ,  H03K3/356 ,  H03K5/08 ,  H03K5/24 ,  H03K5/20 ,  H03F3/16 ,  H04B15/00

CPC classification number: H03K3/356026 ,  H03K3/356095 ,  H03K5/249

Abstract: The voltages to be compared are applied to a passive MOS capacitor differencing circuit for producing a voltage difference signal, which then is amplified by a high-gain non-precision FET amplifier, the output of which is passed through a low output impedance FET buffer amplifier to a FET latching circuit. Capacitive coupling is used for enabling the amplifiers to be independently biased and to eliminate D.C. offsets. The operating cycle of the comparator has two periods. During an initial set-up or preconditioning period the amplifiers are self-biased by appropriate switching actions which cause each of the amplifiers to be set at a desired operating point that is maintained when its respective bias switching connection subsequently is opened. The bias switch openings in the respective amplifier and latching stages are timed to occur in a chosen sequence which causes the switching transients to be absorbed. At the end of the preconditioning period, the comparator is set up for operation in the comparison period during which the input signals are compared.

Abstract translation: 要比较的电压被施加到无源MOS电容差分电路，用于产生电压差信号，然后由高增益非精密FET放大器放大，其输出通过低输出阻抗FET缓冲放大器 到FET闭锁电路。 电容耦合用于使放大器能够被独立地偏置并消除直流偏移。 比较器的工作周期有两个周期。 在初始设置或预处理周期期间，放大器通过合适的切换动作自偏置，这导致每个放大器被设置在当其各自的偏置开关连接随后被打开时保持的期望工作点。 相应放大器和锁存级中的偏置开关开口定时以选择的顺序发生，这导致开关瞬变被吸收。 在预处理周期结束时，比较器设置为在比较输入信号的比较期间进行操作。

公开(公告)号：US3987315A

公开(公告)日：1976-10-19

申请号：US609939

申请日：1975-09-03

Applicant: Shigeki Matsue

Inventor： Shigeki Matsue

IPC: G06F7/00 ,  G11C11/408 ,  H03K3/356 ,  H03K19/0185 ,  H03K19/082 ,  H03K3/286 ,  H03K3/353

CPC classification number: H03K3/356095 ,  G11C11/4082 ,  H03K3/356026

Abstract: An amplifier circuit for amplifying an input signal includes a flip-flop circuit activated by a timing signal. A trigger circuit generates a first trigger signal of the same polarity as the input signal and another circuit generates a second trigger signal of the opposite polarity to the input signal. The flip-flop circuit is triggered by the first and second trigger signals at the same time the flip-flop circuit is activated by the timing signal.

Abstract translation: 用于放大输入信号的放大器电路包括由定时信号激活的触发器电路。 触发电路产生与输入信号相同极性的第一触发信号，另一电路产生与输入信号相反极性的第二触发信号。 触发器电路由第一和第二触发信号触发，同时触发器电路由定时信号激活。

公开(公告)号：US3813564A

公开(公告)日：1974-05-28

申请号：US37376173

申请日：1973-06-26

Applicant: HITACHI LTD

Inventor： HATSUKANO Y ,  NOMIYA K ,  TORII S

IPC: G11C19/28 ,  H03K3/356 ,  H03K3/286

CPC classification number: H03K3/356078 ,  G11C19/28 ,  H03K3/356 ,  H03K3/356026 ,  H03K3/35606

Abstract: A flip-flop circuit includes a first inverter including a first insulated gate field-effect transistor (MISFET), a second MISFET for storage, and a third MISFET for control of writing and a fourth MISFET, the second and third MISFET''s being connected in series between the first and fourth MISFET''s. A fifth MISFET for receiving an input signal and a sixth MISFET for control of writing are connected between the first and fourth MISFET''s. A second inverter including a seventh MISFET for storage and a MISFET for a load thereof are connected in series with each other, an output terminal of the second inverter being feedbackconnected to an input electrode of the second MISFET. An eighth MISFET for transfer is connected between an output terminal of the first inverter and an input electrode of the seventh MISFET. The third MISFET is rendered non-conductive and the sixth MISFET conductive at writing when at least the fourth and eighth MISFET''s are conductive.

Abstract translation: 触发器电路包括：第一反相器，包括第一绝缘栅场效应晶体管（MISFET），用于存储的第二MISFET以及用于写入的第三MISFET和第四MISFET，第二和第三MISFET串联连接 在第一和第四MISFET之间。 用于接收输入信号的第五MISFET和用于写入控制的第六MISFET连接在第一和第四MISFET之间。 包括用于存储的第七MISFET和其负载的MISFET的第二反相器彼此串联连接，第二反相器的输出端被反馈连接到第二MISFET的输入电极。 用于传送的第八MISFET连接在第一反相器的输出端和第七MISFET的输入电极之间。 当至少第四和第八MISFET导电时，第三MISFET被非导电并且第六MISFET在写入时导通。

公开(公告)号：US3813563A

公开(公告)日：1974-05-28

申请号：US37375873

申请日：1973-06-26

Applicant: HITACHI LTD

Inventor： TORII S ,  HATSUKANO Y ,  NOMIYA K

IPC: G11C19/28 ,  H03K3/356 ,  H03K3/286

CPC classification number: H03K3/356078 ,  G11C19/28 ,  H03K3/356 ,  H03K3/356026 ,  H03K3/35606

Abstract: A flip-flop circuit comprising a first inverter including a first insulated gate field-effect transistor (MISFET), a second MISFET for storage and a third MISFET, the second MISFET being connected in series between the first and third MISFET''s; a fourth MISFET for input and a fifth MISFET for control of writing as are connected in series between the first and third MISFET''s; a second inverter including a MISFET for load and a sixth MISFET for storage as are connected in series with each other; a seventh MISFET for transfer as is connected between an output terminal of the first inverter and an input electrode of the sixth MISFET; and an eighth MISFET connected in parallel with the sixth MISFET. An output terminal of the second inverter is feedback-connected to an input electrode of the second MISFET, input electrodes of the third and seventh MISFET''s are applied with a first train of clock pulses, an input electrode of the first MISFET is applied with a second train of clock pulses differing in phase from the first train of clock pulses, an input electrode of the fourth MISFET is applied with an input signal, input electrodes of the fifth and eighth MISFET''s are applied with a writing control signal adapted to render the fifth and eighth MISFET''s conductive at writing when at least the third and seventh MISFET''s are conductive, and an output signal is derived from the input electrode of the sixth MISFET.

Abstract translation: 一种触发器电路，包括：第一反相器，包括第一绝缘栅场效应晶体管（MISFET），第二MISFET和第三MISFET，所述第二MISFET串联连接在所述第一和第三MISFET之间; 用于输入的第四MISFET和用于在第一和第三MISFET之间串联连接的写入控制的第五MISFET; 包括用于负载的MISFET和彼此串联连接的第六MISFET的第二反相器; 第七MISFET，用于连接在第一反相器的输出端和第六MISFET的输入电极之间; 以及与第六MISFET并联连接的第八MISFET。 第二反相器的输出端子反馈连接到第二MISFET的输入电极，第三和第七MISFET的输入电极施加第一列时钟脉冲，第一MISFET的输入电极施加第二 与第一串时钟脉冲相位不同的时钟脉冲序列，第四MISFET的输入电极施加输入信号，第五和第八MISFET的输入电极被施加有写入控制信号，该写入控制信号适于呈现第五和 当至少第三和第七MISFET的导通时，第八MISFET在写入时导通，并且从第六MISFET的输入电极导出输出信号。

公开(公告)号：US11817860B2

公开(公告)日：2023-11-14

申请号：US17647885

申请日：2022-01-13

Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.

Inventor： Yinchuan Gu

IPC: H03K3/35 ,  H03K3/356 ,  H03M1/12 ,  G06F1/08

CPC classification number: H03K3/356026 ,  G06F1/08 ,  H03M1/121 ,  H03M1/1255

Abstract: The present disclosure relates to a dual-clock generation circuit and method and an electronic device, and relates to the technical field of integrated circuits. The dual-clock generation circuit includes: a first inverter module, configured to access a first signal and output a first clock output signal; a second inverter module, configured to access a second signal and output a second clock output signal, where the first signal and the second signal are opposite clock signals; a first feedforward buffer, disposed between an input terminal of the first inverter module and an output terminal of the second inverter module, and configured to transmit the first signal to compensate for the second clock output signal.