公开(公告)号：US4899316A

公开(公告)日：1990-02-06

申请号：US947451

申请日：1986-12-29

Applicant: Akira Nagami

Inventor： Akira Nagami

IPC: G06F12/00 ,  G06F12/04 ,  G06T1/60 ,  G11C7/10 ,  G11C11/401

CPC classification number: G11C7/1075

Abstract: An improved semiconductor memory which can achieve high-speed data processing is disclosed. The memory comprises a memory array, a random access port for accessing a desired one of memory cell in accordance with row and column addresses, a serial read circuit for consecutively reading data from the selected row one by one and a serial write circuit for consecutively writing data to the selected row one by one without specific column address information.

Abstract translation: 公开了一种能够实现高速数据处理的改进的半导体存储器。 存储器包括存储器阵列，用于根据行和列地址访问存储单元中期望的一个存储器阵列的串行读取电路，以及从所选行逐一读取数据的串行读取电路和用于连续写入的串行写入电路 数据到所选行一个一个没有特定的列地址信息。

公开(公告)号：US4442365A

公开(公告)日：1984-04-10

申请号：US326925

申请日：1981-12-02

Applicant: Akira Nagami

Inventor： Akira Nagami

IPC: G11C11/408 ,  H03K3/356 ,  H03K19/0185 ,  H03K19/096

CPC classification number: H03K3/356026 ,  H03K3/356078

Abstract: A latch circuit has first to fourth nodes. The first node is supplied with a logic signal and the second node is charged at a first potential. A potential at the third node is discharged to the second potential. The fourth node is charged to the first potential. This all happens during a first period, after which, and during a second period, a potential at the second node is transferred to the third node. An inverter transistor is responsive to a level of the logic signal at the first node for discharging a potential of the second node to a second potential when the logic signal level is in the first potential and for retaining the first potential of the second node when the logic signal level is in the second potential. A transfer between the fourth and the first nodes is responsive to the second potential at the third node for discharging the potential of the fourth node to the second potential. A true and a complement signals of a large amplitude are established at the fourth and second nodes.

Abstract translation: 锁存电路具有第一至第四节点。 第一个节点被提供一个逻辑信号，第二个节点以第一个电位充电。 第三节点处的电位被放电到第二个电位。 第四个节点被充电到第一个电位。 这全部发生在第一时段期间，之后，在第二时段期间，第二节点处的电位被传送到第三节点。 当逻辑信号电平处于第一电位时，逆变器晶体管响应于第一节点处的逻辑信号的电平，用于将第二节点的电位放电到第二电位，并且当第二节点的第一电位保持在第一电位时， 逻辑信号电平处于第二电位。 第四节点和第一节点之间的传输响应于第三节点处的第二电位，用于将第四节点的电位释放到第二电位。 在第四和第二节点处建立大幅度的真实和补码信号。

公开(公告)号：US4710896A

公开(公告)日：1987-12-01

申请号：US648225

申请日：1984-09-07

Applicant: Akira Nagami

Inventor： Akira Nagami

IPC: G09G5/36 ,  G09G5/00 ,  G11C8/16 ,  G11C11/24

CPC classification number: G11C8/16

Abstract: An improved semiconductor memory, suitable for a video system, includes a memory cell array, a first access circuit operatively performing a write operation and a read operation to the memory cell array, and a second access circuit operatively performing a read operation to the memory cell array in response to different groups of address signals from those applied to the first access circuit. The two access circuits can operate asynchronously and can simultaneously access the memory.

Abstract translation: 适用于视频系统的改进的半导体存储器包括存储单元阵列，对存储单元阵列可操作地执行写入操作和读取操作的第一存取电路以及可操作地对存储单元执行读取操作的第二存取电路 响应于来自应用于第一存取电路的地址信号的不同组的阵列。 两个访问电路可以异步操作，并且可以同时访问存储器。

公开(公告)号：US4570242A

公开(公告)日：1986-02-11

申请号：US436991

申请日：1982-10-27

Applicant: Akira Nagami

Inventor： Akira Nagami

IPC: G11C11/403 ,  G11C11/406 ,  G11C11/407 ,  G11C11/40

CPC classification number: G11C11/406

Abstract: A dynamic memory is capable of performing an internal charge storing refreshing operation with a low power consumption. The memory comprises an inverter for receiving a signal from the outside. The inverter is composed of an input transistor and a load circuit whose ability to feed a current to the input transistor is controllable and is made smaller during the internal refresh operation.

Abstract translation: 动态存储器能够以低功耗执行存储刷新操作的内部电荷。 存储器包括用于从外部接收信号的反相器。 逆变器由输入晶体管和负载电路组成，负载电路能够控制输入晶体管的电流，并在内部刷新操作期间使其变小。

公开(公告)号：US4334295A

公开(公告)日：1982-06-08

申请号：US145537

申请日：1980-05-01

Applicant: Akira Nagami

Inventor： Akira Nagami

IPC: G11C11/403 ,  G11C11/406 ,  G11C11/40

CPC classification number: G11C11/406

Abstract: A two-clock multi-address input dynamic random access memory provided with an internal refresh function for refreshing memory cells without receiving refresh address information from the outside is disclosed. The memory characteristically comprises a terminal for receiving a refresh control signal, refresh address means for designating a row address to be refreshed, means for producing confirmation signal when a reset precharge of a circuit relating to a refresh operation is completed, means for storing the refresh control signal when a row address strobe signal is in active level, and means responsive to the confirmation signal and the stored refresh signal for effecting the refresh operation.

Abstract translation: 公开了一种具有用于刷新存储器单元而不从外部接收刷新地址信息的内部刷新功能的双时钟多地址输入动态随机存取存储器。 存储器特征性地包括用于接收刷新控制信号的终端，用于指定要刷新的行地址的刷新地址装置，当与刷新操作相关的电路的复位预充电完成时产生确认信号的装置，用于存储刷新的装置 当行地址选通信号处于活动电平时，控制信号，以及响应于确认信号和所存储的刷新信号以进行刷新操作的装置。

公开(公告)号：US4149099A

公开(公告)日：1979-04-10

申请号：US831820

申请日：1977-09-09

Applicant: Akira Nagami

Inventor： Akira Nagami

IPC: G11C11/41 ,  G11C11/408 ,  G11C11/413 ,  G11C11/418 ,  H03K3/356 ,  H03K5/15 ,  H03K19/096 ,  H03K3/286 ,  G11C8/00 ,  H03K3/353 ,  H03K5/20

CPC classification number: G11C11/418 ,  G11C11/4082 ,  H03K3/356026 ,  H03K3/356095 ,  H03K5/15

Abstract: An amplifier circuit for amplifying an input signal and obtaining true and complementary output signals includes cross-coupled transistors connected to first and second nodes. The first and second nodes are made to be an equal potential by precharging. Then, the potential of the first node is either maintained or changed to a lower (in absolute value) level in response to and dependently on a control input signal, while the potential of the second node is slightly lowered (in absolute value) by dividing the precharged change of the second node with a capacitor. Thus, the first node is controlled by the input signal, while the second node is given a reference potential determined by a capacitance division ratio.

Abstract translation: 用于放大输入信号并获得真实和互补输出信号的放大器电路包括连接到第一和第二节点的交叉耦合晶体管。 通过预充电使第一和第二节点成为相等的电位。 然后，响应于并且依赖于控制输入信号，第一节点的电位被保持或改变为较低（绝对值）电平，而第二节点的电位被稍微降低（绝对值），除以 用电容器预先充电的第二节点的变化。 因此，第一节点由输入信号控制，而第二节点被给予由电容分压比决定的参考电位。

公开(公告)号：US4090096A

公开(公告)日：1978-05-16

申请号：US782419

申请日：1977-03-29

Applicant: Akira Nagami

Inventor： Akira Nagami

IPC: H03K5/04 ,  G11C11/4076 ,  H03K5/05 ,  H03K5/135 ,  H03K17/28 ,  H03K1/18 ,  G11C8/00 ,  H03K5/01

CPC classification number: G11C11/4076 ,  H03K5/05 ,  H03K5/135

Abstract: A timing signal generator includes a field-effect transistor having a drain supplied with a command signal and a source connected to an output node. The gate of the transistor is connected to a circuit node which is precharged to a voltage to render the transistor conductive prior to the activation of the command signal. A delay circuit having a predetermined delay time has an input connected to the output node and an output connected to a circuit for discharging the output node and the circuit node in response to the output of the delay circuit.

Abstract translation: 定时信号发生器包括具有提供有命令信号的漏极和连接到输出节点的源极的场效应晶体管。 晶体管的栅极连接到电路节点，该电路节点预先充电到电压，以在激活命令信号之前使晶体管导通。 具有预定延迟时间的延迟电路具有连接到输出节点的输入端和连接到电路的输出端，用于响应于延迟电路的输出而对输出节点和电路节点进行放电。

公开(公告)号：US4330719A

公开(公告)日：1982-05-18

申请号：US41433

申请日：1979-05-22

Applicant: Akira Nagami

Inventor： Akira Nagami

IPC: G11C11/407 ,  G11C11/4076 ,  G11C11/4094 ,  H03K5/02 ,  H03K17/06 ,  H03K19/094 ,  H03K19/096 ,  H03K17/687

CPC classification number: G11C11/4094 ,  G11C11/4076 ,  H03K19/096

Abstract: The invention provides for maintaining a charged node point at the potential level of a power source, when the potential must be dynamically sustained. This is done by a circuit using insulated-gate, field-effect transistors. Preferably, two such transistors are used in conjunction with a bootstrap capacitor which changes the potential of a signal appearing at a circuit node responsive to any leaking of current at an output, which might otherwise cause the node potential to drift down to a lower level.

Abstract translation: 本发明提供了当电势必须被动态地维持时，将充电的节点保持在电源的潜在电平。 这是通过使用绝缘栅，场效应晶体管的电路完成的。 优选地，两个这样的晶体管与自举电容器一起使用，该自举电容器响应于输出处的电流的任何泄漏而改变出现在电路节点处的信号的电位，否则可能导致节点电位向下漂移到较低的电平。

公开(公告)号：US4500974A

公开(公告)日：1985-02-19

申请号：US428517

申请日：1982-09-29

Applicant: Akira Nagami

Inventor： Akira Nagami

IPC: G11C11/403 ,  G11C11/406 ,  G11C11/409 ,  G11C11/40

CPC classification number: G11C11/406

Abstract: A memory circuit capable of detecting that refresh operation is surely ended is disclosed. The memory circuit comprises a memory cell matrix, a dummy array sharing rows with the memory cell matrix and similar column structure to the memory cell matrix, and means coupled to a pair of digit lines of the dummy array for detecting that a potential at either of the pair of digit lines in the dummy array reaches an amplified low level.

Abstract translation: 公开了能够检测刷新操作的存储电路。 存储器电路包括存储单元矩阵，与存储单元矩阵共享行的虚拟阵列和与存储单元矩阵相似的列结构，以及耦合到虚拟阵列的一对数字线的装置，用于检测任一个的电位 虚拟阵列中的一对数位线达到放大的低电平。

公开(公告)号：US4397000A

公开(公告)日：1983-08-02

申请号：US225600

申请日：1981-01-19

Applicant: Akira Nagami

Inventor： Akira Nagami

IPC: G11C11/419 ,  G11C11/4076 ,  G11C11/409 ,  G11C11/4093 ,  H03K3/356 ,  G11C7/00

CPC classification number: G11C11/4093 ,  G11C11/4076 ,  H03K3/356

Abstract: An output buffer circuit operable at a high-speed and stably holding output level is disclosed. The output buffer circuit comprises a pair of input transistors receivivable a true and a complementary signals, a pair of output nodes from which amplified signals of the true and complementary signals are derived, a pair of switching gates coupled between the drains of the input transistors and the output nodes and control means for operatively disenabling the switching gates when logic state of the true and complementary signals applied to the input transistors is reversed.

Abstract translation: 公开了一种以高速稳定保持输出电平工作的输出缓冲电路。 输出缓冲器电路包括一对输入晶体管，可接收真实和互补的信号，一对输出节点，从其中导出真实和互补信号的放大信号，耦合在输入晶体管的漏极之间的一对开关栅极和 输出节点和控制装置，用于在施加到输入晶体管的真实和互补信号的逻辑状态相反时，可操作地使开关门断开。