公开(公告)号：US11075159B2

公开(公告)日：2021-07-27

申请号：US16035723

申请日：2018-07-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ching-Yu Huang ,  Han-Ping Pu ,  Ming-Kai Liu ,  Ting-Chu Ko ,  Yung-Ping Chiang ,  Chang-Wen Huang ,  Yu-Sheng Hsieh

IPC: H01L23/00 ,  H01L23/522 ,  H01L21/56 ,  H01L23/31 ,  H01L23/538 ,  H01L23/532 ,  H01L21/768

Abstract: Integrated fan-out packages and methods of forming the same are disclosed. An integrated fan-out package includes two dies, an encapsulant, a first metal line and a plurality of dummy vias. The encapsulant is disposed between the two dies. The first metal line is disposed over the two dies and the encapsulant, and electrically connected to the two dies. The plurality of dummy vias is disposed over the encapsulant and aside the first metal line.

公开(公告)号：US10825773B2

公开(公告)日：2020-11-03

申请号：US16292348

申请日：2019-03-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Chun-Lin Lu ,  Han-Ping Pu ,  Kai-Chiang Wu

IPC: H01L23/12 ,  H01L21/00 ,  H01L21/4763 ,  H01L23/48 ,  H01L23/538 ,  H01L23/00 ,  H01L23/31 ,  H01L23/522 ,  H01L23/528 ,  H01L25/18 ,  H01L21/56

Abstract: A package structure includes an insulating encapsulation, at least one semiconductor die, a redistribution circuit structure, and first reinforcement structures. The at least one semiconductor die is encapsulated in the insulating encapsulation. The redistribution circuit structure is located on the insulating encapsulation and electrically connected to the at least one semiconductor die. The first reinforcement structures are embedded in the redistribution circuit structure. A shape of the package structure includes a polygonal shape on a vertical projection along a stacking direction of the insulating encapsulation and the redistribution circuit structure, and the first reinforcement structures are located on and extended along diagonal lines of the package structure.

公开(公告)号：US20200335459A1

公开(公告)日：2020-10-22

申请号：US16916066

申请日：2020-06-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Albert Wan ,  Ching-Hua Hsieh ,  Chao-Wen Shih ,  Han-Ping Pu ,  Meng-Tse Chen ,  Sheng-Hsiang Chiu

IPC: H01L23/66 ,  H01L23/522 ,  H01L23/31 ,  H01L21/56

Abstract: A semiconductor device including a chip package, a dielectric structure, and a first antenna pattern is provided. The dielectric structure is disposed on the chip package and includes a cavity and a vent in communication with the cavity. The first antenna pattern is disposed on the dielectric structure, wherein the chip package is electrically coupled to the first antenna pattern, and the cavity of the dielectric structure is disposed between the chip package and the first antenna pattern.

公开(公告)号：US10741508B2

公开(公告)日：2020-08-11

申请号：US15965995

申请日：2018-04-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Albert Wan ,  Ching-Hua Hsieh ,  Chao-Wen Shih ,  Han-Ping Pu ,  Meng-Tse Chen ,  Sheng-Hsiang Chiu

IPC: H01L23/66 ,  H01L23/522 ,  H01L23/31 ,  H01L21/56

Abstract: A semiconductor device including a chip package, a dielectric structure and a first antenna pattern is provided. The dielectric structure disposed on the chip package and includes a cavity and a vent in communication with the cavity. The first antenna pattern disposed on the dielectric structure, wherein the chip package is electrically coupled to the first antenna pattern, and the cavity of the dielectric structure is disposed between the chip package and the first antenna pattern. A manufacturing method of a semiconductor device is also provided.

公开(公告)号：US20200243441A1

公开(公告)日：2020-07-30

申请号：US16258652

申请日：2019-01-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Min-Chien Hsiao ,  Chuei-Tang Wang ,  Chao-Wen Shih ,  Han-Ping Pu ,  Chieh-Yen Chen

IPC: H01L23/522 ,  H01L23/00 ,  H01L23/31 ,  H01L23/528 ,  H01L21/56

Abstract: A package structure includes a die, an encapsulant, and a first redistribution structure. The die has an active surface and a rear surface opposite to the active surface. The die includes a ground plane within the die. The encapsulant encapsulates the die. The first redistribution structure is over the active surface of the die. The first redistribution structure includes an antenna pattern electrically coupled with the ground plane. The antenna pattern is electrically connected to the die.

公开(公告)号：US20190157206A1

公开(公告)日：2019-05-23

申请号：US15965980

申请日：2018-04-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chuei-Tang Wang ,  Chung-Hao Tsai ,  Chen-Hua Yu ,  Chun-Lin Lu ,  Chao-Wen Shih ,  Han-Ping Pu ,  Kai-Chiang Wu ,  Albert Wan

IPC: H01L23/538 ,  H01L23/498 ,  H01L25/00 ,  H01L25/065 ,  H01L23/28

CPC classification number: H01L23/5384 ,  H01L21/56 ,  H01L21/6835 ,  H01L23/28 ,  H01L23/3121 ,  H01L23/49816 ,  H01L23/66 ,  H01L24/18 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2221/68372 ,  H01L2221/68381 ,  H01L2224/18

Abstract: A package structure includes a first redistribution layer, a second redistribution layer, at least one semiconductor chip, an insulating encapsulation, a protection layer, and at least one connecting module. The at least one semiconductor chip is located between and electrically connected to the first redistribution layer and the second redistribution layer. The insulating encapsulation encapsulates the at least one semiconductor chip. The protection layer is disposed on and partially covers the first redistribution layer, wherein the first redistribution layer is located between the at least one semiconductor chip and the protection layer. The at least one connecting module connects to the first redistribution layer and is electrically connected to the at least one semiconductor chip through the first redistribution layer, wherein the at least one connecting module comprises a plurality of pins, and the at least one connecting module is mounted onto the first redistribution layer by the protection layer and is accessibly exposed by the protection layer.

公开(公告)号：US10269720B2

公开(公告)日：2019-04-23

申请号：US15360739

申请日：2016-11-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Han-Ping Pu ,  Hsiao-Wen Lee

IPC: H01L23/02 ,  H01L23/538 ,  H01L23/00 ,  H01L21/768 ,  H01L21/683 ,  H01L23/31 ,  H01L21/56 ,  H01L23/498

Abstract: The present disclosure provides a packaged device that includes a first dielectric layer; a second dielectric layer, formed over the first dielectric layer, that includes a device substrate and a via extending from the first dielectric layer and through the second dielectric layer; and a third dielectric layer, formed over the second dielectric layer, that includes a conductive pillar extending through the third dielectric layer, wherein the conductive pillar is electrically coupled to the via of the second dielectric layer.

公开(公告)号：US10256203B2

公开(公告)日：2019-04-09

申请号：US15662261

申请日：2017-07-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Lipu Kris Chuang ,  Han-Ping Pu ,  Hsin-Yu Pan ,  Sen-Kuei Hsu

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/42 ,  H01L23/367 ,  H01L23/538

Abstract: A semiconductor package includes a die, a passivation layer, a plurality of first electrical conductive vias, a plurality of second electrical conductive vias, a plurality of thermal conductive vias and a connecting pattern. The die includes a plurality of first pads and a plurality of second pads. The passivation layer is disposed on the die. The first electrical conductive vias and the second electrical conductive vias extend through the passivation layer and contact the first pads and the second pads respectively. The thermal conductive vias are disposed on the passivation layer. Each of the thermal conductive vias is spaced apart from the first and second electrical conductive vias. The connecting pattern is disposed on the passivation layer and connects the first electrical conductive vias and the thermal conductive vias. The thermal conductive vias are connected to the first pads through the connecting pattern and the first electrical conductive vias.

公开(公告)号：US20190035752A1

公开(公告)日：2019-01-31

申请号：US15662261

申请日：2017-07-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Lipu Kris Chuang ,  Han-Ping Pu ,  Hsin-Yu Pan ,  Sen-Kuei Hsu

IPC: H01L23/00 ,  H01L23/538 ,  H01L23/367 ,  H01L23/31

Abstract: A semiconductor package includes a die, a passivation layer, a plurality of first electrical conductive vias, a plurality of second electrical conductive vias, a plurality of thermal conductive vias and a connecting pattern. The die includes a plurality of first pads and a plurality of second pads. The passivation layer is disposed on the die. The first electrical conductive vias and the second electrical conductive vias extend through the passivation layer and contact the first pads and the second pads respectively. The thermal conductive vias are disposed on the passivation layer. Each of the thermal conductive vias is spaced apart from the first and second electrical conductive vias. The connecting pattern is disposed on the passivation layer and connects the first electrical conductive vias and the thermal conductive vias. The thermal conductive vias are connected to the first pads through the connecting pattern and the first electrical conductive vias.