公开(公告)号：US10096716B2

公开(公告)日：2018-10-09

申请号：US15271504

申请日：2016-09-21

Applicant: Samsung Display Co., Ltd.

Inventor： Yu-Gwang Jeong ,  Hyun Min Cho ,  Su Bin Bae ,  Shin Il Choi

IPC: H01L29/10 ,  H01L29/12 ,  H01L29/786 ,  H01L27/12

Abstract: A thin film transistor array panel includes a substrate; a data line disposed on the substrate; a buffer layer disposed on the substrate and spaced apart from the data line in a plan view; a thin film transistor disposed on the buffer layer, the thin film transistor including an oxide semiconductor layer; and a pixel electrode connected to the thin film transistor.

公开(公告)号：US09704896B2

公开(公告)日：2017-07-11

申请号：US15004392

申请日：2016-01-22

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Duk-Sung Kim ,  Shin Il Choi ,  Su Bin Bae ,  Yu-Gwang Jeong

IPC: H01L27/12 ,  G02F1/1362 ,  G02F1/1335 ,  G02F1/1333 ,  G02F1/1343

CPC classification number: H01L27/1259 ,  G02F1/1333 ,  G02F1/133345 ,  G02F1/133516 ,  G02F1/134309 ,  G02F1/136227 ,  G02F1/136286 ,  G02F2001/134372 ,  G02F2001/136222 ,  H01L27/1237 ,  H01L27/124 ,  H01L27/1248 ,  H01L27/1262

Abstract: A manufacturing method includes forming a gate member and a common electrode line on a substrate. A gate insulating layer is formed on the gate member and the common electrode line. A semiconductor member and a data member are formed on the gate insulating layer. A first passivation layer is formed on the semiconductor member and the data member. A plurality of color filters is formed on the first passivation layer. A conductor layer and a second passivation layer are formed on the plurality of color filters. A first contact hole exposes a common electrode. A second contact hole exposes the drain electrode. The first and second contact holes are formed by a photolithography process. A pixel electrode connected to the drain electrode is formed through the first contact hole. A connecting member connected to the common electrode line and the common electrode is formed through the second contact hole.

公开(公告)号：US09640566B2

公开(公告)日：2017-05-02

申请号：US14487300

申请日：2014-09-16

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Ji-Young Park ,  Yu-Gwang Jeong ,  Sang Gab Kim ,  Joon Geol Lee

IPC: G02F1/136 ,  H01L27/12 ,  H01L29/786 ,  H01L29/66 ,  G02F1/1343 ,  G02F1/1362

CPC classification number: H01L27/1259 ,  G02F1/134363 ,  G02F1/136227 ,  H01L27/124 ,  H01L29/66765 ,  H01L29/78669 ,  H01L29/78678

Abstract: A thin film transistor array panel includes a substrate, gate lines, each including a gate pad, a gate insulating layer, data lines, each including a data pad connected to a source and drain electrode, a first passivation layer disposed on the data lines and the drain electrode, a first electric field generating electrode, a second passivation layer disposed on the first electric field generating electrode, and a second electric field generating electrode. The gate insulating layer and the first and second passivation layers include a first contact hole exposing a part of the gate pad, the first and second passivation layers include a second contact hole exposing a part of the data pad, and at least one of the first and second contact holes have a positive taper structure having a wider area at an upper side than at a lower side.

公开(公告)号：US09443879B2

公开(公告)日：2016-09-13

申请号：US14455113

申请日：2014-08-08

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Yu-Gwang Jeong ,  Shin-Il Choi ,  Su-Bin Bae ,  Dae-Ho Kim ,  Sang-Gab Kim ,  Jae-Neung Kim

IPC: H01L27/12 ,  H01L21/311 ,  H01L21/768

CPC classification number: H01L27/124 ,  H01L21/31116 ,  H01L21/76804 ,  H01L21/76832 ,  H01L27/1259

Abstract: A display substrate includes a base substrate, a common line on the base substrate, a first insulation layer covering the common line and having a first insulating material, a conductive pattern on the first insulation layer and including a source electrode and a drain electrode, a second insulation layer covering the drain electrode and the common line, and including a lower second insulation layer having a second insulating material and an upper second insulation layer having the first insulating material, a first electrode electrically connected to the drain electrode through a first contact hole in the second insulation layer, and a second electrode electrically connected to the common line through a second contact hole in the first and second insulation layers. The upper and lower second insulation layers on the drain electrode have a first hole and a second hole respectively that form the first contact hole.

Abstract translation: 显示基板包括基底基板，基底基板上的公共线，覆盖公共线的第一绝缘层，并具有第一绝缘材料，第一绝缘层上的导电图案，包括源电极和漏电极， 覆盖漏电极和公共线的第二绝缘层，并且包括具有第二绝缘材料的下第二绝缘层和具有第一绝缘材料的上第二绝缘层，第一电极，通过第一接触孔电连接到漏电极 以及通过第一绝缘层和第二绝缘层中的第二接触孔与公共线电连接的第二电极。 漏电极上的上，下第二绝缘层分别具有形成第一接触孔的第一孔和第二孔。

公开(公告)号：US09379252B2

公开(公告)日：2016-06-28

申请号：US14666461

申请日：2015-03-24

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Yong Su Lee ,  Yoon Ho Khang ,  Dong Jo Kim ,  Hyun Jae Na ,  Sang Ho Park ,  Se Hwan Yu ,  Chong Sup Chang ,  Dae Ho Kim ,  Jae Neung Kim ,  Myoung Geun Cha ,  Sang Gab Kim ,  Yu-Gwang Jeong

IPC: H01L27/00 ,  H01L29/00 ,  H01L29/786 ,  H01L27/12 ,  H01L29/66 ,  H01L29/417

CPC classification number: H01L29/78633 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1288 ,  H01L27/3262 ,  H01L29/41733 ,  H01L29/66969 ,  H01L29/78618 ,  H01L29/7869 ,  H01L29/78696

Abstract: A thin film transistor according to an exemplary embodiment of the present invention includes an oxide semiconductor. A source electrode and a drain electrode face each other. The source electrode and the drain electrode are positioned at two opposite sides, respectively, of the oxide semiconductor. A low conductive region is positioned between the source electrode or the drain electrode and the oxide semiconductor. An insulating layer is positioned on the oxide semiconductor and the low conductive region. A gate electrode is positioned on the insulating layer. The insulating layer covers the oxide semiconductor and the low conductive region. A carrier concentration of the low conductive region is lower than a carrier concentration of the source electrode or the drain electrode.

Abstract translation: 根据本发明的示例性实施例的薄膜晶体管包括氧化物半导体。 源电极和漏电极彼此面对。 源电极和漏电极分别位于氧化物半导体的两个相对侧。 低导电区域位于源电极或漏电极与氧化物半导体之间。 绝缘层位于氧化物半导体和低导电区域上。 栅电极位于绝缘层上。 绝缘层覆盖氧化物半导体和低导电区域。 低导电区域的载流子浓度低于源电极或漏电极的载流子浓度。

公开(公告)号：US09224764B2

公开(公告)日：2015-12-29

申请号：US14468633

申请日：2014-08-26

Applicant: Samsung Display Co., LTD.

Inventor： Jae-Neung Kim ,  Yu-Gwang Jeong ,  Shin-Il Choi ,  Dae-Ho Kim ,  Myoung-Geun Cha ,  Sang-Gab Kim ,  Jung-Ha Son

IPC: H01L27/14 ,  H01L27/12

CPC classification number: H01L27/1262 ,  H01L27/1218 ,  H01L27/124

Abstract: A display substrate includes a data pad on a base substrate, a first buffer layer which covers the data pad, a second buffer layer pattern which is disposed on the first buffer layer and separated from the data pad in a plan view, an active layer on the second buffer layer pattern, a gate insulation layer pattern on the active layer, both ends of the active layer exposed by the gate insulation layer pattern, and a gate electrode on the gate insulation layer pattern.

Abstract translation: 显示基板包括在基底基板上的数据焊盘，覆盖数据焊盘的第一缓冲层，布置在第一缓冲层上并在平面图中与数据焊盘分离的第二缓冲层图案，活性层 第二缓冲层图案，有源层上的栅极绝缘层图案，由栅极绝缘层图案曝光的有源层的两端以及栅极绝缘层图案上的栅极电极。

公开(公告)号：US20150179802A1

公开(公告)日：2015-06-25

申请号：US14527632

申请日：2014-10-29

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Jae-Neung Kim ,  Shin-Il Choi ,  Yu-Gwang Jeong ,  Su-Bin Bae ,  Dae-Ho Kim ,  Sang-Gab Kim

IPC: H01L29/786 ,  H01L29/66 ,  H01L27/12

CPC classification number: H01L29/7869 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1259 ,  H01L29/41733 ,  H01L29/45 ,  H01L29/66969 ,  H01L29/78606

Abstract: A thin film transistor includes a gate electrode, an active pattern over the gate electrode and including an oxide semiconductor, an etch-stop layer covering the active pattern, a source electrode on the etch-stop layer, a drain electrode on the etch-stop layer and spaced from the source electrode, and an active protection pattern between the etch-stop layer and the active pattern and electrically coupled to the source electrode and the drain electrode.

Abstract translation: 薄膜晶体管包括栅电极，栅电极上的有源图案，并且包括氧化物半导体，覆盖有源图案的蚀刻停止层，蚀刻停止层上的源电极，蚀刻停止层上的漏电极 层，并且与源电极间隔开，以及蚀刻停止层和有源图案之间的电耦合到源电极和漏电极的有源保护图案。

公开(公告)号：US08987047B2

公开(公告)日：2015-03-24

申请号：US14184361

申请日：2014-02-19

Applicant: Samsung Display Co., Ltd.

Inventor： Yong Su Lee ,  Yoon Ho Khang ,  Dong Jo Kim ,  Hyun Jae Na ,  Sang Ho Park ,  Se Hwan Yu ,  Chong Sup Chang ,  Dae Ho Kim ,  Jae Neung Kim ,  Myoung Geun Cha ,  Sang Gab Kim ,  Yu-Gwang Jeong

IPC: H01L21/00 ,  H01L29/10 ,  H01L29/786 ,  H01L27/12 ,  H01L29/66

CPC classification number: H01L29/78633 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1288 ,  H01L27/3262 ,  H01L29/41733 ,  H01L29/66969 ,  H01L29/78618 ,  H01L29/7869 ,  H01L29/78696

Abstract: A thin film transistor according to an exemplary embodiment of the present invention includes an oxide semiconductor. A source electrode and a drain electrode face each other. The source electrode and the drain electrode are positioned at two opposite sides, respectively, of the oxide semiconductor. A low conductive region is positioned between the source electrode or the drain electrode and the oxide semiconductor. An insulating layer is positioned on the oxide semiconductor and the low conductive region. A gate electrode is positioned on the insulating layer. The insulating layer covers the oxide semiconductor and the low conductive region. A carrier concentration of the low conductive region is lower than a carrier concentration of the source electrode or the drain electrode.

Abstract translation: 根据本发明的示例性实施例的薄膜晶体管包括氧化物半导体。 源电极和漏电极彼此面对。 源电极和漏电极分别位于氧化物半导体的两个相对侧。 低导电区域位于源电极或漏电极与氧化物半导体之间。 绝缘层位于氧化物半导体和低导电区域上。 栅电极位于绝缘层上。 绝缘层覆盖氧化物半导体和低导电区域。 低导电区域的载流子浓度低于源电极或漏电极的载流子浓度。