公开(公告)号：US20140264610A1

公开(公告)日：2014-09-18

申请号：US13799955

申请日：2013-03-13

Applicant: QUALCOMM INCORPORATED

Inventor： Bin Yang ,  Xia Li ,  PR Chidambaram

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/6681 ,  H01L21/7624 ,  H01L21/765 ,  H01L21/823842 ,  H01L21/823878 ,  H01L27/0207 ,  H01L29/785

Abstract: Embodiments disclosed in the detailed description include metal oxide semiconductor (MOS) isolation schemes with continuous active areas separated by dummy gates. A MOS device includes an active area formed from a material with a work function that is described as either an n-metal or a p-metal. Active components are formed on this active area using materials having a similar work function. Isolation is effectuated by positioning a dummy gate between the active components. The dummy gate is made from a material having an opposite work function relative to the material of the active area. For example, if the active area was a p-metal material, the dummy gate would be made from an n-metal, and vice versa.

Abstract translation: 在详细描述中公开的实施例包括具有由伪栅极分开的连续有效区域的金属氧化物半导体（MOS）隔离方案。 MOS器件包括由具有作为n金属或p金属的功函数的材料形成的有源区域。 使用具有类似功函数的材料在该有效区域上形成活性组分。 通过在有源部件之间定位一个虚拟栅极来实现隔离。 虚拟门由相对于有源区的材料具有相反功函数的材料制成。 例如，如果有源区域是p金属材料，则虚拟栅极将由n金属制成，反之亦然。

公开(公告)号：US08836079B2

公开(公告)日：2014-09-16

申请号：US13748768

申请日：2013-01-24

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Bin Yang

IPC: H01L21/02

CPC classification number: H01L28/60 ,  H01L23/5223 ,  H01L28/88 ,  H01L28/91 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Metal-on-Metal (MoM) capacitors having laterally displaced layers and related systems and methods are disclosed. In one embodiment, a MoM capacitor includes a plurality of vertically stacked layers that are laterally displaced relative to one another. Lateral displacement of the layers minimizes cumulative surface process variations making a more reliable and uniform capacitor.

Abstract translation: 公开了具有横向移位层的金属对金属（MoM）电容器及相关系统和方法。 在一个实施例中，MoM电容器包括相对于彼此横向移位的多个垂直堆叠的层。 层的横向位移最小化累积的表面处理变化，从而形成更可靠和更均匀的电容器。

公开(公告)号：US20140203404A1

公开(公告)日：2014-07-24

申请号：US13745962

申请日：2013-01-21

Applicant: QUALCOMM INCORPORATED

Inventor： Jihong Choi ,  John J. Zhu ,  PR Chidambaram ,  Bin Yang ,  Lixin Ge

IPC: H01L49/02

CPC classification number: H01L28/87 ,  H01L23/5223 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Spiral metal-on-metal (MoM or SMoM) capacitors and related systems and methods of forming MoM capacitors are disclosed. In one embodiment, a MoM capacitor disposed in a semiconductor die is disclosed. The MoM capacitor comprises a first electrode coupled to a first trace. The first trace is coiled in a first inwardly spiraling pattern and comprised of first parallel trace segments. The MoM capacitor also comprises a second electrode coupled to a second trace. The second trace is coiled in the first inwardly spiraling pattern and comprised of second parallel trace segments interdisposed between the first parallel trace segments. Reduced variations in the capacitance allow circuit designers to build circuits with tighter tolerances and generally improve circuit reliability.

Abstract translation: 公开了形成MoM电容器的螺旋金属金属（MoM或SMoM）电容器及相关系统和方法。 在一个实施例中，公开了一种设置在半导体管芯中的MoM电容器。 MoM电容器包括耦合到第一迹线的第一电极。 第一迹线卷绕在第一向内螺旋形的图案中并由第一平行迹线段组成。 MoM电容器还包括耦合到第二迹线的第二电极。 第二迹线卷绕在第一向内螺旋形图案中，并且包括间隔在第一平行迹线段之间的第二平行迹线段。 降低电容的变化允许电路设计者构建更严格公差的电路，并且通常提高电路的可靠性。

公开(公告)号：US20140197519A1

公开(公告)日：2014-07-17

申请号：US13743388

申请日：2013-01-17

Applicant: QUALCOMM INCORPORATED

Inventor： Jihong Choi ,  John J. Zhu ,  PR Chidambaram ,  Bin Yang ,  Lixin Ge

IPC: H01L49/02 ,  G06F17/50

CPC classification number: H01L28/92

Abstract: In a particular embodiment, a method of forming a metal-insulator-metal (MIM) capacitor includes removing, using a lithographic mask, a first portion of an optical planarization layer to expose a region in which the MIM capacitor is to be formed. A second portion of an insulating layer is formed on a first conductive layer that is formed on a plurality of trench surfaces within the region. The method further includes removing at least a third portion of the insulating layer according to a lift-off technique.

Abstract translation: 在特定实施例中，形成金属 - 绝缘体 - 金属（MIM）电容器的方法包括使用光刻掩模去除光学平坦化层的第一部分以暴露其中将形成MIM电容器的区域。 绝缘层的第二部分形成在形成在该区域内的多个沟槽表面上的第一导电层上。 该方法还包括根据剥离技术去除绝缘层的至少第三部分。

公开(公告)号：US20130320494A1

公开(公告)日：2013-12-05

申请号：US13721089

申请日：2012-12-20

Applicant: QUALCOMM INCORPORATED

Inventor： John J. Zhu ,  PR Chidambaram ,  Lixin Ge ,  Bin Yang ,  Jihong Choi

IPC: H01L49/02

CPC classification number: H01L28/40 ,  H01L23/5223 ,  H01L27/0207 ,  H01L28/86 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor die having a plurality of metal layers, including a set of metal layers having a preferred direction for minimum feature size. The set of metal layers are such that adjacent metal layers have preferred directions orthogonal to one another. Finger capacitors formed in the set of metal layers are such that a finger capacitor formed in one metal layer has a finger direction parallel to the preferred direction of that metal layer. In bidirectional metal layers, capacitor fingers may be in either direction.

Abstract translation: 一种具有多个金属层的半导体管芯，包括一组具有最小特征尺寸的优选方向的金属层。 金属层的组合使得相邻的金属层具有彼此正交的优选方向。 形成在金属层组中的手指电容器使得形成在一个金属层中的手指电容器具有平行于该金属层的优选方向的手指方向。 在双向金属层中，电容指可以在任一方向上。

公开(公告)号：US12206001B2

公开(公告)日：2025-01-21

申请号：US16526756

申请日：2019-07-30

Applicant: QUALCOMM Incorporated

Inventor： Bin Yang ,  Haining Yang ,  Xia Li

IPC: H01L29/423 ,  H01L21/762 ,  H01L21/8234 ,  H01L27/088

Abstract: A semiconductor device is disclosed that includes a plurality of fins on a substrate. A long channel gate is disposed over a first portion of the plurality of fins. A gate contact is provided having an extended portion that extends into an active area from a gate contact base outside the active area.

公开(公告)号：US11545483B2

公开(公告)日：2023-01-03

申请号：US16712222

申请日：2019-12-12

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Haining Yang ,  Bin Yang

IPC: H01L27/06 ,  H01L29/04 ,  H01L29/06 ,  H01L29/66 ,  H01L21/8238 ,  H01L21/762 ,  H01L29/78

Abstract: Certain aspects of the present disclosure are directed to a semiconductor device. The semiconductor device generally includes a substrate, at least one silicon-on-insulator (SOI) transistor disposed above the substrate, a gate-all-around (GAA) transistor disposed above the substrate, and a fin field-effect transistor (FinFET) disposed above the substrate.

公开(公告)号：US11515406B2

公开(公告)日：2022-11-29

申请号：US16379904

申请日：2019-04-10

Applicant: QUALCOMM Incorporated

Inventor： Gengming Tao ,  Bin Yang ,  Xia Li

IPC: H01L29/737 ,  H01L29/40 ,  H01L29/66 ,  H03F3/19

Abstract: Aspects generally relate to a heterojunction bipolar transistor (HBT), and method of manufacturing the same. The HBT including an emitter a first, a first side of a base coupled to a second side of the emitter opposite the first side of the emitter. A collector coupled to the base on a second side of the base opposite the emitter, wherein an area of a junction between the base and the collector is less than or equal to an area of a junction between the base and the emitter. A dielectric coupled to the collector. A first conductive base contact coupled to the base and adjacent to the collector and extending over a base-collector junction, the conductive base contact operative as a field plate.

公开(公告)号：US10930730B2

公开(公告)日：2021-02-23

申请号：US15816295

申请日：2017-11-17

Applicant: QUALCOMM Incorporated

Inventor： Ye Lu ,  Yun Yue ,  Phanikumar Konkapaka ,  Bin Yang ,  Chuan-Hsing Chen

IPC: H01L23/52 ,  H01L27/08 ,  H01L29/06 ,  H01L23/522 ,  H01L29/78 ,  H01L29/93

Abstract: A metal-oxide-semiconductor (MOS) device for radio frequency (RF) applications may include a guard ring. The guard ring may surround the MOS device and at least one other MOS device. The MOS device may further include a level zero contact layer coupled to a first interconnect layer through level zero interconnects and vias. The first interconnect layer may be for routing to the MOS device.

公开(公告)号：US10923436B2

公开(公告)日：2021-02-16

申请号：US16362951

申请日：2019-03-25

Applicant: QUALCOMM Incorporated

Inventor： Bin Yang ,  Kai Liu ,  Xia Li

IPC: H01L23/00 ,  H01L25/16 ,  H01L23/498 ,  H04W88/02 ,  H04W88/08

Abstract: Certain aspects of the present disclosure provide apparatus for thermal matching of integrated circuits (ICs). One example apparatus generally includes a first substrate, a first IC disposed on the first substrate and having a second substrate, and a second IC disposed on the first substrate. The second IC may include a third substrate, a thermal conductivity adjustment region comprising different material than the third substrate, the thermal conductivity adjustment region being adjacent to a first side of the third substrate, and one or more electrical components formed in one or more layers of the second IC adjacent to a second side of the third substrate, wherein the first side and the second side are opposite sides of the third substrate, and wherein a thermal conductivity of the thermal conductivity adjustment region is closer to a thermal conductivity of the second substrate than a thermal conductivity of the third substrate.