公开(公告)号：US09324779B2

公开(公告)日：2016-04-26

申请号：US14063934

申请日：2013-10-25

Applicant: QUALCOMM Incorporated

Inventor： Young Kyu Song ,  Daeik Daniel Kim ,  Jonghae Kim ,  Xiaonan Zhang ,  Ryan David Lane ,  Mario Francisco Velez ,  Chengjie Zuo ,  Changhan Hobie Yun

IPC: H01L49/02 ,  H01L23/522 ,  H01L23/64

CPC classification number: H01L28/10 ,  H01L23/5227 ,  H01L23/645 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/00

Abstract: Some novel features pertain to an integrated device that includes a substrate, a first cavity through the substrate, and a toroid inductor configured around the first cavity of the substrate. The toroid inductor includes a set of windings configured around the first cavity. The set of windings includes a first set of interconnects on a first surface of the substrate, a set of though substrate vias (TSVs), and a second set of interconnects on a second surface of the substrate. The first set of interconnects is coupled to the second set of interconnects through the set TSVs. In some implementations, the integrated device further includes an interconnect material (e.g., solder ball) located within the first cavity. The interconnect material is configured to couple a die to a printed circuit board. In some implementations, the interconnect material is part of the toroid inductor.

Abstract translation: 一些新颖的特征涉及包括衬底，通过衬底的第一腔和围绕衬底的第一腔配置的环形电感器的集成器件。 环形电感器包括围绕第一腔配置的一组绕组。 该组绕组包括在衬底的第一表面上的第一组互连，一组通过衬底通孔（TSV）和在衬底的第二表面上的第二组互连。 第一组互连通过集合TSV耦合到第二组互连。 在一些实施方案中，集成器件还包括位于第一腔内的互连材料（例如，焊球）。 互连材料被配置为将管芯耦合到印刷电路板。 在一些实施方案中，互连材料是环形电感器的一部分。

公开(公告)号：US09245940B2

公开(公告)日：2016-01-26

申请号：US14179202

申请日：2014-02-12

Applicant: QUALCOMM Incorporated

Inventor： Young Kyu Song ,  Yunseo Park ,  Xiaonan Zhang ,  Ryan David Lane ,  Aristotele Hadjichristos

IPC: H01L27/08 ,  H01L49/02 ,  H01L23/00 ,  H01L23/522

CPC classification number: H01L28/10 ,  H01L23/3192 ,  H01L23/5227 ,  H01L24/02 ,  H01L24/05 ,  H01L24/13 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05147 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/13006 ,  H01L2224/16225 ,  H01L2924/01029 ,  H01L2924/30107

Abstract: An inductor design on a wafer level package (WLP) does not need to depopulate the solder balls on the die because the solder balls form part of the inductor. One terminal on the inductor couples to the die, the other terminal couples to a single solder ball on the die, and the remaining solder balls that mechanically contact the inductor remain electrically floating. The resulting device has better inductance, direct current (DC) resistance, board-level reliability (BLR), and quality factor (Q).

Abstract translation: 晶圆级封装（WLP）上的电感器设计不需要将焊球沉淀在芯片上，因为焊球形成电感器的一部分。 电感器上的一个端子耦合到管芯，另一个端子耦合到管芯上的单个焊球，并且与电感器机械接触的剩余焊球保持电浮动。 所产生的器件具有更好的电感，直流（DC）电阻，电路板级可靠性（BLR）和品质因数（Q）。

公开(公告)号：US20150325375A1

公开(公告)日：2015-11-12

申请号：US14272356

申请日：2014-05-07

Applicant: QUALCOMM Incorporated

Inventor： Young Kyu Song ,  Kyu-Pyung Hwang ,  Dong Wook Kim ,  Xiaonan Zhang ,  Ryan David Lane

IPC: H01G4/30 ,  H05K3/46 ,  H05K1/11 ,  H01G2/02 ,  H05K1/18

CPC classification number: H01G4/236 ,  H01G2/02 ,  H01G2/106 ,  H01G4/224 ,  H01G4/30 ,  H01G4/33 ,  H01G4/40 ,  H05K1/0231 ,  H05K1/115 ,  H05K1/182 ,  H05K1/185 ,  H05K3/4644 ,  H05K3/4697 ,  H05K2201/10015 ,  Y10T29/42

Abstract: Some novel features pertain to package substrates that include a substrate having an embedded package substrate (EPS) capacitor with equivalent series resistance (ESR) control. The EPS capacitor includes two conductive electrodes separated by a dielectric or insulative thin film material and an equivalent series resistance (ESR) control structure located on top of each electrode connecting the electrodes to vias. The ESR control structure may include a metal layer, a dielectric layer, and a set of metal pillars which are embedded in the set of metal pillars are embedded in the dielectric layer and extend between the electrode and the metal layer. The EPS capacitor having the ESR control structure form an ESR configurable EPS capacitor which can be embedded in package substrates.

Abstract translation: 一些新颖的特征涉及包括具有等效串联电阻（ESR）控制的嵌入式封装衬底（EPS）电容器的衬底的封装衬底。 EPS电容器包括由电介质或绝缘薄膜材料隔开的两个导电电极和位于将电极连接到通孔的每个电极顶部的等效串联电阻（ESR）控制结构。 ESR控制结构可以包括金属层，电介质层和嵌入金属柱组中的一组金属柱，其嵌入电介质层并在电极和金属层之间延伸。 具有ESR控制结构的EPS电容器形成可嵌入封装衬底的ESR可配置EPS电容器。

公开(公告)号：US20150294791A1

公开(公告)日：2015-10-15

申请号：US14252695

申请日：2014-04-14

Applicant: QUALCOMM Incorporated

Inventor： Kyu-Pyung Hwang ,  Hong Bok We ,  Young Kyu Song ,  Dong Wook Kim

IPC: H01G4/30 ,  H05K1/18 ,  H01G4/005 ,  H05K1/02 ,  H01L23/00 ,  H01G4/12

CPC classification number: H01G4/30 ,  H01G4/008 ,  H01G4/12 ,  H01G4/1227 ,  H01G4/232 ,  H01G4/33 ,  H01L24/32 ,  H01L24/83 ,  H01L2224/16225 ,  H01L2224/32265 ,  H01L2224/83801 ,  H01L2924/1205 ,  H01L2924/15311 ,  H05K1/0231 ,  H05K3/3436 ,  H05K2201/10015 ,  H05K2201/10378 ,  H05K2201/10515

Abstract: A ceramic capacitor is provided that includes a first capacitor surface, a second opposing capacitor surface, and metal plates perpendicular to the first capacitor surface and second opposing capacitor surface. The metal plates extend from the first capacitor surface to the second opposing capacitor surface. The ceramic capacitor is capable of being interposed between a die and a substrate. A portion of the metal plates are capable of being coupled to conductive pads of the die on the first capacitor surface and to conductive pads of the substrate on the second capacitor surface.

Abstract translation: 提供一种陶瓷电容器，其包括第一电容器表面，第二相对电容器表面和垂直于第一电容器表面和第二相对电容器表面的金属板。 金属板从第一电容器表面延伸到第二相对的电容器表面。 陶瓷电容器能够插入在管芯和衬底之间。 金属板的一部分能够耦合到第一电容器表面上的管芯的导电焊盘和第二电容器表面上的衬底的导电焊盘。

公开(公告)号：US20150130024A1

公开(公告)日：2015-05-14

申请号：US14079503

申请日：2013-11-13

Applicant: QUALCOMM Incorporated

Inventor： Young Kyu Song ,  Kyu-Pyung Hwang ,  Dong Wook Kim ,  Changhan Hobie Yun

IPC: H01L27/08 ,  H01L49/02

CPC classification number: H01L28/40 ,  H01G2/06 ,  H01G4/012 ,  H01G4/12 ,  H01G4/1227 ,  H01G4/30 ,  H01G4/306 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5223 ,  H01L23/642 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L25/16 ,  H01L27/0805 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/16267 ,  H01L2224/81815 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19103 ,  H01L2924/014

Abstract: A multilayer capacitor is provided that includes a plurality of vias configured to receive interconnects from a die.

Abstract translation: 提供了一种层叠电容器，其包括多个通孔，其构造成从模具接收互连。

公开(公告)号：US20140319652A1

公开(公告)日：2014-10-30

申请号：US14323907

申请日：2014-07-03

Applicant: QUALCOMM Incorporated

Inventor： Jong-Hoon Lee ,  Young Kyu Song ,  Jung Ho Yoon ,  Uei Ming Jow ,  Xiaonan Zhang ,  Ryan David Lane

IPC: H01L23/522 ,  H01L49/02

CPC classification number: H01L23/5227 ,  H01L23/5223 ,  H01L23/525 ,  H01L23/645 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L25/03 ,  H01L25/0657 ,  H01L25/074 ,  H01L25/117 ,  H01L28/10 ,  H01L28/40 ,  H01L2224/02375 ,  H01L2224/0239 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0346 ,  H01L2224/03616 ,  H01L2224/0401 ,  H01L2224/05569 ,  H01L2224/05647 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/81447 ,  H01L2225/06562 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/1431 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/15331 ,  H01L2924/15788 ,  H01L2924/19105 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/00012 ,  H01L2924/00

Abstract: Some implementations provide an integrated device that includes a capacitor and an inductor. The inductor is electrically coupled to the capacitor. The inductor and the capacitor are configured to operate as a filter for an electrical signal in the integrated device. The inductor includes a first metal layer of a printed circuit board (PCB), a set of solder balls coupled to the PCB, and a second metal layer in a die. In some implementations, the capacitor is located in the die. In some implementations, the capacitor is a surface mounted passive device on the PCB. In some implementations, the first metal layer is a trace on the PCB. In some implementations, the inductor includes a third metal layer in the die. In some implementations, the second metal layer is an under bump metallization (UBM) layer of the die, and the third metal is a redistribution layer of the die.

Abstract translation: 一些实施方案提供了包括电容器和电感器的集成器件。 电感器电耦合到电容器。 电感器和电容器被配置为在集成器件中用作电信号的滤波器。 电感器包括印刷电路板（PCB）的第一金属层，耦合到PCB的一组焊球，以及模具中的第二金属层。 在一些实施方案中，电容器位于管芯中。 在一些实现中，电容器是PCB上的表面安装无源器件。 在一些实施方案中，第一金属层是PCB上的痕迹。 在一些实施方案中，电感器包括管芯中的第三金属层。 在一些实施方案中，第二金属层是管芯的凸块下金属化（UBM）层，第三金属是管芯的再分布层。

公开(公告)号：US10256863B2

公开(公告)日：2019-04-09

申请号：US15151285

申请日：2016-05-10

Applicant: QUALCOMM INCORPORATED

Inventor： Shiqun Gu ,  Chengjie Zuo ,  Steve Fanelli ,  Thomas Gee ,  Young Kyu Song

IPC: H04B1/48 ,  H01L21/84 ,  H01L23/48 ,  H01L23/60 ,  H01L23/66 ,  H01L27/12 ,  H01L29/06 ,  H01L49/02 ,  H01L21/762 ,  H01L21/768 ,  H01L23/522

Abstract: An integrated radio frequency (RF) circuit structure may include a resistive substrate material and a switch. The switch may be arranged in a silicon on insulator (SOI) layer supported by the resistive substrate material. The integrated RF circuit structure may also include an isolation layer coupled to the SOI layer. The integrated RF circuit structure may further include a filter, composed of inductors and capacitors. The filter may be arranged on a surface of the integrated RF circuit structure, opposite the resistive substrate material. In addition, the switch may be arranged on a first surface of the isolation layer.

公开(公告)号：US10051741B2

公开(公告)日：2018-08-14

申请号：US14073756

申请日：2013-11-06

Applicant: QUALCOMM Incorporated

Inventor： Young Kyu Song ,  Daeik Daniel Kim ,  Xiaonan Zhang ,  Ryan David Lane ,  Jonghae Kim

IPC: H05K1/18 ,  H05K1/16 ,  H05K1/14

Abstract: An embedded layered inductor is provided that includes a first inductor layer and a second inductor layer coupled to the first inductor layer. The first inductor layer comprises a patterned metal layer that may also be patterned to form pads. The second inductor layer comprises metal deposited in a dielectric layer adjacent the patterned metal layer.

公开(公告)号：US10049977B2

公开(公告)日：2018-08-14

申请号：US14450201

申请日：2014-08-01

Applicant: QUALCOMM Incorporated

Inventor： Hong Bok We ,  Dong Wook Kim ,  Jae Sik Lee ,  Kyu-Pyung Hwang ,  Young Kyu Song

IPC: H01L23/495 ,  H01L23/498 ,  H01L25/10 ,  H01L21/48 ,  H01L23/31 ,  H01L25/065 ,  H01L23/538

Abstract: A package on package structure may be formed by fabricating or providing a bottom package having a substrate, at least one die on top of the substrate, and bonding pads on the top of the substrate. Next, a frame is formed on the bonding pads and connected to the bonding pads. Next, a package material is molded over the top of the substrate to encapsulate the frame, the die, and the pads or substantially encapsulates these components. Next, a portion of the molded package material is removed to expose at least a portion of the frame. The exposed frame portions are formed such that a desired fan in or fan out configuration is obtained. Next, a non-conductive layer is formed on the exposed frame. Last, a second package having a die or chip is connected to the exposed portion of the frame to form a package on package structure.

公开(公告)号：US09875997B2

公开(公告)日：2018-01-23

申请号：US14572753

申请日：2014-12-16

Applicant: QUALCOMM Incorporated

Inventor： Hong Bok We ,  Dong Wook Kim ,  Kyu-Pyung Hwang ,  Young Kyu Song

IPC: H01L25/10 ,  H01L23/14 ,  H01L25/00 ,  H01L23/13 ,  H01L23/538 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L25/105 ,  H01L23/13 ,  H01L23/142 ,  H01L23/3128 ,  H01L23/5389 ,  H01L23/562 ,  H01L24/19 ,  H01L24/20 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/24247 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/8203 ,  H01L2224/83192 ,  H01L2224/92244 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2924/15153 ,  H01L2924/15155 ,  H01L2924/15311 ,  H01L2924/15724 ,  H01L2924/15747 ,  H01L2924/3511

Abstract: The present disclosure provides semiconductor packages and methods for fabricating PoP semiconductor packages. The PoP semiconductor package may comprise a first semiconductor package, the first semiconductor package comprising an anodized metal lid structure comprising (i) a central cavity having a central cavity opening direction and (ii) at least one perimeter cavity having a perimeter cavity opening direction facing in an opposite direction of the central cavity opening direction, a first semiconductor device arranged in the central cavity of the anodized metal lid structure, a redistribution layer electrically coupled to the first semiconductor device, wherein a conductive trace formed in the redistribution layer is exposed to the at least one perimeter cavity, and solder material arranged in the at least one perimeter cavity, and a second semiconductor package, the second semiconductor package comprising at least one conductive post, wherein the at least one conductive post is electrically coupled to the solder material arranged in the at least one perimeter cavity.