公开(公告)号：US20150092469A1

公开(公告)日：2015-04-02

申请号：US14040332

申请日：2013-09-27

Applicant: QUALCOMM Incorporated

Inventor： Taehyun Kim ,  Jung Pill Kim ,  Sungryul Kim

IPC: G11C11/16 ,  G11C13/00

CPC classification number: G11C11/1673 ,  G11C7/14 ,  G11C11/15 ,  G11C11/16 ,  G11C11/1675 ,  G11C13/0002 ,  G11C13/004 ,  G11C29/021 ,  G11C29/028 ,  G11C2013/0042 ,  G11C2013/0054

Abstract: A system and method to trim reference levels in a resistive memory is disclosed. In a particular embodiment, a resistive memory includes multiple sets of reference cells. The resistive memory also includes a reference resistance measurement circuit. A first set of reference cells is accessible by the reference resistance measurement circuit to measure a first effective reference resistance corresponding to the first set of reference cells. A second set of reference cells is accessible by the reference resistance measurement circuit to measure a second effective reference resistance corresponding to the second set of reference cells. The resistive memory also includes a trimming circuit configured to set a reference resistance based on the measured first effective resistance and the measured second effective resistance.

Abstract translation: 公开了一种在电阻性存储器中修整参考电平的系统和方法。 在特定实施例中，电阻性存储器包括多组参考单元。 电阻存储器还包括参考电阻测量电路。 第一组参考单元可由参考电阻测量电路访问，以测量对应于第一组参考单元的第一有效参考电阻。 第二组参考单元可由参考电阻测量电路访问，以测量对应于第二组参考单元的第二有效参考电阻。 电阻存储器还包括修整电路，其被配置为基于测量的第一有效电阻和所测量的第二有效电阻来设置参考电阻。

公开(公告)号：US20150070978A1

公开(公告)日：2015-03-12

申请号：US14021674

申请日：2013-09-09

Applicant: QUALCOMM Incorporated

Inventor： Taehyun Kim ,  Jung Pill Kim ,  Sungryul Kim

IPC: G11C11/16

CPC classification number: G11C11/1673 ,  G11C7/062 ,  G11C7/14 ,  G11C11/1659 ,  G11C13/0069

Abstract: An apparatus includes a group of data cells and a reference cell coupled to the group of data cells. The reference cell includes four magnetic tunnel junction (MTJ) cells. Each of the four MTJ cells is coupled to a distinct word line. Each of the four MTJ cells includes an MTJ element and a single transistor. The single transistor of each particular MTJ cell is configured to enable read access to the MTJ element of the particular MTJ cell.

Abstract translation: 一种装置包括一组数据单元和耦合到该组数据单元的参考单元。 参考单元包括四个磁隧道结（MTJ）单元。 四个MTJ单元中的每一个耦合到不同的字线。 四个MTJ单元中的每一个包括MTJ元件和单个晶体管。 每个特定MTJ单元的单个晶体管被配置为使得能够读取访问特定MTJ单元的MTJ元件。

公开(公告)号：US08929167B2

公开(公告)日：2015-01-06

申请号：US13756136

申请日：2013-01-31

Applicant: QUALCOMM Incorporated

Inventor： Jung Pill Kim ,  Taehyun Kim ,  Xia Li ,  Seung H. Kang

IPC: G11C29/00 ,  G11C11/00 ,  G11C7/10 ,  G11C29/44 ,  G11C11/16 ,  G11C11/15 ,  G11C11/155 ,  G11C29/12

CPC classification number: G11C29/4401 ,  G11C11/15 ,  G11C11/155 ,  G11C11/16 ,  G11C11/165 ,  G11C11/1675 ,  G11C29/12 ,  G11C2029/1208 ,  G11C2029/4402

Abstract: Memory self-repair circuitry includes a memory cell array on a chip, and built-in self test (BIST) circuitry on the chip coupled to the memory cell array. The BIST circuitry is configured to perform a magnetic random access memory (MRAM) write operation to write addresses of failed memory cells in the memory cell array to a failed address sector also in the memory cell array. The memory self-repair circuitry also includes first select circuitry coupled between the BIST circuitry and the memory cell array. The first select circuitry is configured to selectively couple an output of the BIST circuitry and an input to the memory cell array.

Abstract translation: 存储器自修复电路包括芯片上的存储单元阵列，以及耦合到存储单元阵列的芯片上的内置自测试（BIST）电路。 BIST电路被配置为执行磁随机存取存储器（MRAM）写入操作，以将存储器单元阵列中的故障存储器单元的地址写入存储器单元阵列中的故障地址扇区。 存储器自修复电路还包括耦合在BIST电路和存储单元阵列之间的第一选择电路。 第一选择电路被配置为选择性地将BIST电路的输出和输入耦合到存储单元阵列。

公开(公告)号：US20140327105A1

公开(公告)日：2014-11-06

申请号：US13887723

申请日：2013-05-06

Applicant: QUALCOMM INCORPORATED

Inventor： Vidhya Ramachandran ,  Brian M. Henderson ,  Shiqun Gu ,  Chiew-Guan Tan ,  Jung Pill Kim ,  Taehyun Kim

IPC: H01L29/66 ,  H01L23/498 ,  H01L29/861

CPC classification number: H01L29/66128 ,  H01L21/304 ,  H01L21/762 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/525 ,  H01L23/535 ,  H01L23/60 ,  H01L25/0657 ,  H01L27/0255 ,  H01L27/0296 ,  H01L27/0694 ,  H01L27/0814 ,  H01L29/0649 ,  H01L29/66143 ,  H01L29/8611 ,  H01L29/872 ,  H01L2224/02372 ,  H01L2224/0239 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/0557 ,  H01L2224/11002 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/16145 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/12032 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A method includes thinning a back-side of a substrate to expose a portion of a first via that is formed in the substrate. The method also includes forming a first diode at the back-side of the substrate. The first diode is coupled to the first via.

Abstract translation: 一种方法包括使衬底的背面变薄以暴露形成在衬底中的第一通孔的一部分。 该方法还包括在衬底的背面形成第一二极管。 第一二极管耦合到第一通孔。

公开(公告)号：US20140211551A1

公开(公告)日：2014-07-31

申请号：US13756136

申请日：2013-01-31

Applicant: QUALCOMM INCORPORATED

Inventor： Jung Pill Kim ,  Taehyun Kim ,  Xia Li ,  Seung H. Kang

IPC: G11C29/44 ,  G11C11/16

CPC classification number: G11C29/4401 ,  G11C11/15 ,  G11C11/155 ,  G11C11/16 ,  G11C11/165 ,  G11C11/1675 ,  G11C29/12 ,  G11C2029/1208 ,  G11C2029/4402

Abstract: Memory self-repair circuitry includes a memory cell array on a chip, and built-in self test (BIST) circuitry on the chip coupled to the memory cell array. The BIST circuitry is configured to perform a magnetic random access memory (MRAM) write operation to write addresses of failed memory cells in the memory cell array to a failed address sector also in the memory cell array. The memory self-repair circuitry also includes first select circuitry coupled between the BIST circuitry and the memory cell array. The first select circuitry is configured to selectively couple an output of the BIST circuitry and an input to the memory cell array.

Abstract translation: 存储器自修复电路包括芯片上的存储单元阵列，以及耦合到存储单元阵列的芯片上的内置自测试（BIST）电路。 BIST电路被配置为执行磁随机存取存储器（MRAM）写入操作，以将存储器单元阵列中的故障存储器单元的地址写入存储器单元阵列中的故障地址扇区。 存储器自修复电路还包括耦合在BIST电路和存储单元阵列之间的第一选择电路。 第一选择电路被配置为选择性地将BIST电路的输出和输入耦合到存储单元阵列。

公开(公告)号：US20140133216A1

公开(公告)日：2014-05-15

申请号：US14161850

申请日：2014-01-23

Applicant: QUALCOMM Incorporated

Inventor： Jung Pill Kim ,  Taehyun Kim

IPC: G11C13/00

CPC classification number: G11C13/004 ,  G11C5/063 ,  G11C7/08 ,  G11C11/1673 ,  G11C13/0038 ,  G11C13/0069 ,  G11C29/026 ,  G11C29/028 ,  G11C2013/0054

Abstract: A memory has a plurality of non-volatile resistive (NVR) memory arrays, each with an associated reference voltage generating circuit coupled by a reference circuit coupling link to a reference line, the reference coupled to a sense amplifier for that NVR memory array. Reference line coupling links couple the reference lines of different NVR memory arrays. Optionally, different ones of the reference coupling links are removed or opened, obtaining respective different average and isolated reference voltages on the different reference lines. Optionally, different ones of the reference circuit coupling links are removed or opened, obtaining respective different averaged voltages on the reference lines, and uncoupling and isolating different reference circuits.

Abstract translation: 存储器具有多个非易失性电阻（NVR）存储器阵列，每个存储阵列具有通过参考电路耦合到参考线的参考电压产生电路，该参考电压产生电路耦合到用于该NVR存储器阵列的读出放大器。 参考线耦合链路耦合不同NVR存储器阵列的参考线。 可选地，不同的参考耦合链路被去除或打开，在不同的参考线上获得各自不同的平均和隔离参考电压。 可选地，去除或打开不同的参考电路耦合链路，在参考线上获得各自不同的平均电压，以及解耦和隔离不同的参考电路。