公开(公告)号：US11991458B2

公开(公告)日：2024-05-21

申请号：US17934196

申请日：2022-09-21

Applicant: OMNIVISION TECHNOLOGIES, INC.

Inventor： Lihang Fan ,  Nijun Jiang ,  Rui Wang

IPC: H04N25/75 ,  H03M1/12 ,  H03M1/18 ,  H04N23/76 ,  H04N25/78

CPC classification number: H04N23/76 ,  H03M1/12 ,  H03M1/18 ,  H03M1/183 ,  H04N25/75 ,  H04N25/78

Abstract: An arithmetic logic unit (ALU) includes a front end latch stage coupled to a signal latch stage coupled to a Gray code (GC) to binary stage. First inputs of an adder stage are coupled to receive outputs of the GC to binary stage. Outputs of the adder stage are generated in response to the first inputs and second inputs of the adder stage. A pre-latch stage is coupled to latch outputs of the adder stage. A feedback latch stage is coupled to latch outputs of the pre-latch stage. The second inputs of the adder stage are coupled to receive outputs of the feedback latch stage. The feedback stage includes first conversion gain feedback latches configured to latch outputs of the pre-latch stage having a first conversion gain and second conversion gain feedback latches configured to latch outputs of the pre-latch stage having a second conversion gain.

公开(公告)号：US20240129650A1

公开(公告)日：2024-04-18

申请号：US18047588

申请日：2022-10-18

Applicant: OMNIVISION TECHNOLOGIES, INC.

Inventor： Rui Wang

IPC: H04N25/772 ,  G06F7/501 ,  G06F7/57

CPC classification number: H04N25/772 ,  G06F7/501 ,  G06F7/57

Abstract: An arithmetic logic unit (ALU) includes a front end latch stage coupled to a signal latch stage coupled to a Gray code (GC) to binary stage. First inputs of an adder stage are coupled to receive outputs of the GC to binary stage. An adder input latch stage includes first and second adder input latches including first and second inputs coupled to receive outputs of the GC to binary stage. An adder input multiplexer stage includes an output coupled to second inputs of the adder stage, and first and second inputs coupled to outputs the first and second adder input latches, respectively.

公开(公告)号：US11683607B2

公开(公告)日：2023-06-20

申请号：US17342383

申请日：2021-06-08

Applicant: OMNIVISION TECHNOLOGIES, INC.

Inventor： Chengcheng Xu ,  Rui Wang ,  Wei Deng ,  Chun-Sheng Yang ,  Xueqing Wang

IPC: H04N25/75 ,  H01L27/146 ,  H01L27/148 ,  H04N25/704 ,  H04N25/772 ,  H04N25/44 ,  H04N25/778

CPC classification number: H04N25/75 ,  H01L27/14612 ,  H01L27/14643 ,  H01L27/14831 ,  H04N25/704 ,  H04N25/772

Abstract: An imaging device includes a plurality of photodiodes arranged in a photodiode array to generate charge in response to incident light. The plurality of photodiodes includes first and second photodiodes. A shared floating diffusion receives charge transferred from the first and second photodiodes. An analog to digital converter (ADC) performs a first ADC conversion to generate a reference readout in response to charge in the shared floating diffusion after a reset operation. The ADC is next performs a second ADC conversion to generate a first half of a phase detection autofocus (PDAF) readout in response to charge transferred from the first photodiode to the shared floating diffusion. The ADC then performs a third ADC conversion to generate a full image readout in response to charge transferred from the second photodiode combined with the charge transferred previously from the first photodiode in the shared floating diffusion.

公开(公告)号：US11683602B1

公开(公告)日：2023-06-20

申请号：US17716856

申请日：2022-04-08

Applicant: OMNIVISION TECHNOLOGIES, INC.

Inventor： Sangjoo Lee ,  Rui Wang ,  Xuelian Liu ,  Min Qu ,  Liang Zuo ,  Selcuk Sen ,  Hiroaki Ebihara ,  Lihang Fan

IPC: H04N25/615 ,  H04N25/133 ,  H04N25/13 ,  H04N25/447

CPC classification number: H04N25/6153 ,  H04N25/133 ,  H04N25/134 ,  H04N25/447

Abstract: An imaging device includes a pixel array of 1×3 pixel circuits that include 3 photodiodes in a column. Bitlines are coupled to the 1×3 pixel circuits. The bitlines are divided into groupings of 3 bitlines per column of the 1×3 pixel circuits. Each column of the 1×3 pixel circuits includes a plurality of first banks coupled to a first bitline, a plurality of second banks coupled to a second bitline, and a plurality of third banks coupled to a third bitline of a respective grouping of the 3 bitlines. The 1×3 pixel circuits are arranged into groupings of 3 1×3 pixel circuits per nine cell pixel structures that form a plurality of 3×3 pixel structures of the pixel array.

公开(公告)号：US11658202B2

公开(公告)日：2023-05-23

申请号：US17066200

申请日：2020-10-08

Applicant: OMNIVISION TECHNOLOGIES, INC.

Inventor： Tiejun Dai ,  Hiroaki Ebihara ,  Sang Joo Lee ,  Rui Wang ,  Hiroki Ui

IPC: H04N5/232 ,  H01L27/146 ,  H01L27/148 ,  H04N23/84 ,  H04N25/13 ,  H04N25/46 ,  H04N25/75 ,  H04N25/77

CPC classification number: H01L27/14645 ,  H01L27/14612 ,  H01L27/14641 ,  H01L27/14812 ,  H01L27/14831 ,  H01L27/14868 ,  H04N23/84 ,  H04N25/13 ,  H04N25/46 ,  H04N25/75 ,  H04N25/77 ,  H01L27/14621

Abstract: A pixel array includes pixel cells, each including photodiodes. A source follower is coupled to generate an image signal in response image charge generated by the photodiodes. A first row select transistor is coupled to the source follower to output the image signal of the pixel cell. Pixel cells are organized into columns including a first column and a second column. The first row select transistors of the pixel cells of the first and second columns of pixel cells are coupled to first and second column bitlines, respectively. The pixel cells of the second column of pixel cells further include a second row select transistor coupled to the source follower to output the respective image signal to the first column bitline.

公开(公告)号：US11652131B2

公开(公告)日：2023-05-16

申请号：US17066277

申请日：2020-10-08

Applicant: OMNIVISION TECHNOLOGIES, INC.

Inventor： Sang Joo Lee ,  Rui Wang ,  Hiroaki Ebihara ,  Tiejun Dai ,  Hiroki Ui

IPC: H01L27/146 ,  H04N5/378 ,  H04N5/374 ,  H01L27/148 ,  H04N9/04 ,  H04N5/347 ,  H04N5/3745

CPC classification number: H01L27/14645 ,  H01L27/14612 ,  H01L27/14641 ,  H01L27/14812 ,  H01L27/14831 ,  H01L27/14868 ,  H04N5/347 ,  H04N5/378 ,  H04N5/3745 ,  H04N9/0451 ,  H04N9/04551 ,  H01L27/14621

Abstract: A pixel array includes pixel cells disposed in semiconductor material. Each of the pixel cells includes photodiodes, and a floating diffusion to receive image charge from the photodiodes. A source follower is coupled to the floating diffusion to generate an image signal in response image charge from the photodiodes. Drain regions of first and second row select transistors are coupled to a source of the source follower. A common junction is disposed in the semiconductor material between gates of the first and second row select transistors such that the drains of the first and second row select transistors are shared and coupled together through the semiconductor material of the common junction. The pixel cells are organized into a rows and columns with bitlines.

公开(公告)号：US11463640B1

公开(公告)日：2022-10-04

申请号：US17339701

申请日：2021-06-04

Applicant: OMNIVISION TECHNOLOGIES, INC.

Inventor： Rui Wang ,  Zheng Yang

IPC: H04N5/347 ,  H04N5/369 ,  H04N5/374 ,  H04N5/378 ,  H04N5/232 ,  H04N5/3745

Abstract: An imaging device includes pixel circuits that include either image sensing photodiodes or phase detection autofocus (PDAF) photodiodes. The PDAF photodiodes are included in a first PDAF pixel circuit included in a first grouping of rows, and a second PDAF pixel circuit included in a second grouping of rows of a pixel array. Bitline pairs are coupled to respective columns of the pixel array. Each bitline pair includes a first bitline coupled to the first grouping of rows and a second bitline coupled to the second grouping of rows of respective columns of the pixel array. Multiplexers are configured to select one of respective first or second bitlines of each bitline pair. A PDAF multiplexer is coupled to a PDAF select signal and the second PDAF circuit through a respective bitline pair. The remaining multiplexers are coupled to a select signal and are coupled to remaining bitline pairs.

公开(公告)号：US11356626B2

公开(公告)日：2022-06-07

申请号：US16855850

申请日：2020-04-22

Applicant: OMNIVISION TECHNOLOGIES, INC.

Inventor： Rui Wang ,  Eiichi Funatsu ,  Woon Il Choi ,  Keiji Mabuchi ,  Chin Poh Pang ,  Qingfei Chen ,  Da Meng ,  Vivian Wang

IPC: H04N5/369 ,  H01L27/146 ,  H04N5/355 ,  H04N5/378

Abstract: An imaging device includes a photodiode array. The photodiodes include a first set of photodiodes configured as image sensing photodiodes and a second set of photodiodes configured as phase detection auto focus (PDAF) photodiodes. The PDAF photodiodes are arranged in at least pairs in neighboring columns and are interspersed among the image sensing photodiodes. Transfer transistors are coupled to corresponding photodiodes. The transfer transistors coupled to the image sensing photodiodes included in an active row of are controlled in response to a first transfer control signal or a second transfer control signal that control all of the image sensing photodiodes of the active row. A transfer transistor is coupled to one of a pair of the PDAF photodiodes of the active row. The first transfer transistor is controlled in response to a first PDAF control signal that is independent of the first or second transfer control signals.

公开(公告)号：US20210337144A1

公开(公告)日：2021-10-28

申请号：US16855850

申请日：2020-04-22

Applicant: OMNIVISION TECHNOLOGIES, INC.

Inventor： Rui Wang ,  Eiichi Funatsu ,  Woon Il Choi ,  Keiji Mabuchi ,  Chin Poh Pang ,  Qingfei Chen ,  Da Meng ,  Vivian Wang

IPC: H04N5/369 ,  H01L27/146 ,  H04N5/355 ,  H04N5/378

Abstract: An imaging device includes a photodiode array. The photodiodes include a first set of photodiodes configured as image sensing photodiodes and a second set of photodiodes configured as phase detection auto focus (PDAF) photodiodes. The PDAF photodiodes are arranged in at least pairs in neighboring columns and are interspersed among the image sensing photodiodes. Transfer transistors are coupled to corresponding photodiodes. The transfer transistors coupled to the image sensing photodiodes included in an active row of are controlled in response to a first transfer control signal or a second transfer control signal that control all of the image sensing photodiodes of the active row. A transfer transistor is coupled to one of a pair of the PDAF photodiodes of the active row. The first transfer transistor is controlled in response to a first PDAF control signal that is independent of the first or second transfer control signals.

公开(公告)号：US20210152756A1

公开(公告)日：2021-05-20

申请号：US16685663

申请日：2019-11-15

Applicant: OMNIVISION TECHNOLOGIES, INC.

Inventor： Rui Wang ,  Hiroaki Ebihara ,  Zhiyong Zhan ,  Liang Zuo ,  Min Qu ,  Wanqing Xin ,  Xuelian Liu

IPC: H04N5/341 ,  H04N5/351 ,  H04N5/378

Abstract: An image sensor includes a pixel array with rows and columns of pixels. Each row of the pixel array has a first end that is opposite a second end of each row of the pixel array. Control circuitry is coupled to the first end of each row of the pixel array to provide control signals to each row of the pixel array from the first end of each row of the pixel array. Far end driver circuitry coupled to the second end of each row of the pixel array to selectively further drive from the second end of each row of the pixel array the control signals provided by the control circuitry from the first end of each row of the pixel array. The control circuitry is further coupled to provide far end control signals to the far end driver circuitry.