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公开(公告)号：US20210329185A1
公开(公告)日：2021-10-21
申请号：US16854765
申请日：2020-04-21
发明人： Lihang Fan , Min Qu , Yu-Shen Yang , Charles Qingle Wu
摘要： A readout circuit for use in an image sensor includes a plurality of comparators. Each one of the plurality of comparators is coupled to receive a ramp signal and a respective analog image data signal from a respective one of a plurality of column bit lines to generate a respective comparator output. Each one of a plurality of arithmetic logic units (ALUs) is coupled to receive phase-aligned Gray code (GC) outputs generated by a GC generator. Each one of the plurality of ALUs is further coupled to a respective one of the plurality of comparators to receive the respective comparator output. Each one of the plurality of ALUs is coupled to latch the phase-aligned GC outputs in response to the respective comparator output to generate a respective digital image data signal.
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公开(公告)号：US11431939B1
公开(公告)日：2022-08-30
申请号：US17217935
申请日：2021-03-30
发明人： Lihang Fan , Nijun Jiang , Liang Zuo , Yuedan Li , Min Qu
摘要： A clock control circuit of an ADC includes a plurality of fractional divider circuits, each including a programmable integer divider coupled to receive an enable skew signal, a clock signal, and an output integer signal to divide down the clock signal by a factor responsive to the output integer signal to generate a fractional divider signal. A delta-sigma modulator is coupled to receive a fractional modulus signal, an input integer signal, and the fractional divider signal to generate the output integer signal, which is a varying signal each cycle and having a long term average DC value substantially equal to a fractional divider ratio K. An extended gain control circuit is coupled to receive the fractional divider signal from each of the fractional divider circuits to generate a plurality of ramp clock signals with adjustable frequencies to adjust a gain setting of a ramp generator of the ADC.
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3.发明公开公开(公告)号：US20230328405A1
公开(公告)日：2023-10-12
申请号：US17658559
申请日：2022-04-08
发明人： Xuelian Liu , Min Qu , Liang Zuo , Selcuk Sen , Hiroaki Ebihara , Rui Wang , Lihang Fan
CPC分类号： H04N5/3698 , H04N5/36961 , H04N5/378
摘要： An imaging device includes a pixel array of pixel circuits arranged in rows and columns. Bitlines are coupled to the pixel circuits. Clamp circuits are coupled to the bitlines. Each of the clamp circuits includes a clamp short transistor to a power line and a respective one of the bitlines. The clamp short transistor is configured to be switched in response to a clamp short enable signal. A first diode drop device is coupled to the power line. A clamp idle transistor is coupled to the first diode drop device such that the first diode drop device and the clamp idle transistor are coupled between the power line and the respective one of the bitlines. The clamp idle transistor is configured to be switched in response to a clamp idle enable signal.
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公开(公告)号：US11595030B2
公开(公告)日：2023-02-28
申请号：US16867399
申请日：2020-05-05
发明人： Lihang Fan , Liang Zuo , Nijun Jiang , Min Qu , Xuelian Liu
摘要： A ramp generator providing ramp signal with high resolution fine gain includes a current mirror having a first and second paths to conduct a capacitor current and an integrator current responsive to the capacitor current. First and second switched capacitor circuits are coupled to the first path. A fractional divider circuit is coupled to receive a clock signal to generate in response to an adjustable fractional divider ratio K a switched capacitor control signal that oscillates between first and second states to control the first and second switched capacitor circuits. The first and second switched capacitor circuits are coupled to be alternatingly charged by the capacitor current and discharged in response to each the switched capacitor control signal. An integrator coupled is to the second path to generate the ramp signal in response to the integrator current.
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公开(公告)号：US20240334085A1
公开(公告)日：2024-10-03
申请号：US18295207
申请日：2023-04-03
发明人： Rui Wang , Chengcheng Xu , Lihang Fan , Eiichi Funatsu
IPC分类号： H04N25/704 , G02B5/20 , H04N25/13 , H04N25/44 , H04N25/78
CPC分类号： H04N25/704 , G02B5/201 , H04N25/134 , H04N25/44 , H04N25/78
摘要： An imaging device includes a pixel array with 2×2 pixel circuits arranged in rows and columns. Each 2×2 pixel circuit includes 4 photodiodes. Bitlines are coupled to the 2×2 pixel circuits and a color filter array is disposed over photodiodes of the pixel array. The color filter array includes color filters having a first color, color filters having a second color, color filters having a third color. The photodiodes of each 2×2 pixel circuits are covered by one of the color filters. Photodiodes covered by color filters having the first color and photodiodes covered by color filters having the second color are configured to provide non-phase detection (non-PD) information. Photodiodes covered by color filters having the third color are configured to provide phase detection (PD) information. Half of the 2×2 pixel circuits have the photodiodes covered by color filters having the third color.
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公开(公告)号：US12088937B2
公开(公告)日：2024-09-10
申请号：US17658559
申请日：2022-04-08
发明人： Xuelian Liu , Min Qu , Liang Zuo , Selcuk Sen , Hiroaki Ebihara , Rui Wang , Lihang Fan
IPC分类号： H04N25/709 , H04N25/78 , H04N25/704 , H04N25/75
CPC分类号： H04N25/709 , H04N25/78 , H04N25/704 , H04N25/75
摘要： An imaging device includes a pixel array of pixel circuits arranged in rows and columns. Bitlines are coupled to the pixel circuits. Clamp circuits are coupled to the bitlines. Each of the clamp circuits includes a clamp short transistor to a power line and a respective one of the bitlines. The clamp short transistor is configured to be switched in response to a clamp short enable signal. A first diode drop device is coupled to the power line. A clamp idle transistor is coupled to the first diode drop device such that the first diode drop device and the clamp idle transistor are coupled between the power line and the respective one of the bitlines. The clamp idle transistor is configured to be switched in response to a clamp idle enable signal.
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公开(公告)号：US11991458B2
公开(公告)日：2024-05-21
申请号：US17934196
申请日：2022-09-21
发明人： Lihang Fan , Nijun Jiang , Rui Wang
摘要： An arithmetic logic unit (ALU) includes a front end latch stage coupled to a signal latch stage coupled to a Gray code (GC) to binary stage. First inputs of an adder stage are coupled to receive outputs of the GC to binary stage. Outputs of the adder stage are generated in response to the first inputs and second inputs of the adder stage. A pre-latch stage is coupled to latch outputs of the adder stage. A feedback latch stage is coupled to latch outputs of the pre-latch stage. The second inputs of the adder stage are coupled to receive outputs of the feedback latch stage. The feedback stage includes first conversion gain feedback latches configured to latch outputs of the pre-latch stage having a first conversion gain and second conversion gain feedback latches configured to latch outputs of the pre-latch stage having a second conversion gain.
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公开(公告)号：US11683602B1
公开(公告)日：2023-06-20
申请号：US17716856
申请日：2022-04-08
发明人： Sangjoo Lee , Rui Wang , Xuelian Liu , Min Qu , Liang Zuo , Selcuk Sen , Hiroaki Ebihara , Lihang Fan
IPC分类号： H04N25/615 , H04N25/133 , H04N25/13 , H04N25/447
CPC分类号： H04N25/6153 , H04N25/133 , H04N25/134 , H04N25/447
摘要： An imaging device includes a pixel array of 1×3 pixel circuits that include 3 photodiodes in a column. Bitlines are coupled to the 1×3 pixel circuits. The bitlines are divided into groupings of 3 bitlines per column of the 1×3 pixel circuits. Each column of the 1×3 pixel circuits includes a plurality of first banks coupled to a first bitline, a plurality of second banks coupled to a second bitline, and a plurality of third banks coupled to a third bitline of a respective grouping of the 3 bitlines. The 1×3 pixel circuits are arranged into groupings of 3 1×3 pixel circuits per nine cell pixel structures that form a plurality of 3×3 pixel structures of the pixel array.
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公开(公告)号：US11632512B2
公开(公告)日：2023-04-18
申请号：US17180520
申请日：2021-02-19
发明人： Lihang Fan , Min Qu , Chao-Fang Tsai , Chun-Hsiang Chang
摘要： An arithmetic logic unit (ALU) includes a front end latch stage coupled to latch Gray code (GC) outputs of a GC generator in response to a comparator output. A signal latch stage is coupled to latch outputs of the front end latch stage. A GC to binary stage is coupled to generate a binary representation of the GC outputs latched in the signal latch stage. First inputs of an adder stage are coupled to receive outputs of the GC to binary stage. Outputs of the adder stage are generated in response to the first inputs and second inputs of the adder stage. A pre-latch stage is coupled to latch outputs of the adder stage. A feedback latch stage is coupled to latch outputs of the pre-latch stage. The second inputs of the adder stage are coupled to receive outputs of the feedback latch stage.
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公开(公告)号：US11431936B2
公开(公告)日：2022-08-30
申请号：US16854765
申请日：2020-04-21
发明人： Lihang Fan , Min Qu , Yu-Shen Yang , Charles Qingle Wu
摘要： A readout circuit for use in an image sensor includes a plurality of comparators. Each one of the plurality of comparators is coupled to receive a ramp signal and a respective analog image data signal from a respective one of a plurality of column bit lines to generate a respective comparator output. Each one of a plurality of arithmetic logic units (ALUs) is coupled to receive phase-aligned Gray code (GC) outputs generated by a GC generator. Each one of the plurality of ALUs is further coupled to a respective one of the plurality of comparators to receive the respective comparator output. Each one of the plurality of ALUs is coupled to latch the phase-aligned GC outputs in response to the respective comparator output to generate a respective digital image data signal.
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