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公开(公告)号：US20240397236A1
公开(公告)日：2024-11-28
申请号：US18322408
申请日：2023-05-23
Applicant: OMNIVISION TECHNOLOGIES, INC.
Inventor： Hiroaki Ebihara , Jiayu Guo , Liang Zuo , Lihang Fan
IPC: H04N25/78 , H04N25/616
Abstract: A readout circuit includes a comparator having a first input coupled to receive a ramp signal from a ramp generator and a second input coupled to receive an analog image data signal from one of a plurality of bitlines. The comparator is configured to generate a comparator output in response to a comparison of the ramp signal and the analog image data signal. A sampling circuit has a first input coupled to receive a sampling control signal and a second input coupled to receive the comparator output. The sampling circuit is configured to generate a sampling output. A counter has a first input coupled to receive a counter control signal and a second input coupled to receive one of the comparator output and a signal from the sampling circuit. The readout circuit is configured to perform correlated multiple sampling (CMS) calculations or non-CMS calculations in response to the sampling output.
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公开(公告)号：US11722801B1
公开(公告)日：2023-08-08
申请号：US17659042
申请日：2022-04-13
Applicant: OMNIVISION TECHNOLOGIES, INC.
Inventor： Hiroaki Ebihara , Zhenfu Tian , Tao Sun , Liang Zuo , Yu-Shen Yang , Satoshi Sakurai , Rui Wang
IPC: H04N25/75 , H04N25/772
CPC classification number: H04N25/75 , H04N25/772
Abstract: A ramp buffer circuit includes an input device having an input coupled to receive a ramp signal. A bias current source is coupled to an output of the input device. The input device and the bias current source are coupled between a power line and ground. An assist current source is coupled between the output of the input device and ground. The assist current source is configured to conduct an assist current from the output of the input device to ground only during a ramp event generated in the ramp signal.
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公开(公告)号：US11218659B2
公开(公告)日：2022-01-04
申请号：US16708135
申请日：2019-12-09
Applicant: OMNIVISION TECHNOLOGIES, INC.
Inventor： Chengcheng Xu , Rui Wang , Bi Yuan , Liang Zuo
Abstract: An image sensing device includes an image sensing circuit, a voltage supply grid, bitlines, and a control circuit. The image sensing circuit includes pixels arranged in rows and columns. Each one of the bitlines is coupled to a corresponding one of the columns. The voltage supply grid is coupled to the pixels. The control circuit is coupled to output at least a row select signal and a transfer signal to the rows. Each one of the rows is selectively coupled to the bitlines to selectively output image data signals in response to the row select signal and the transfer signal. Each one of the rows is further selectively coupled to the bitlines to selectively clamp the bitlines in response to the row select signal and the transfer signal. Each one of the rows is selectively decoupled from the bitlines in response to the row select signal.
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公开(公告)号：US20210351768A1
公开(公告)日：2021-11-11
申请号：US16867399
申请日：2020-05-05
Applicant: OMNIVISION TECHNOLOGIES, INC.
Inventor： Lihang Fan , Liang Zuo , Nijun Jiang , Min Qu , Xuelian Liu
Abstract: A ramp generator providing ramp signal with high resolution fine gain includes a current mirror having a first and second paths to conduct a capacitor current and an integrator current responsive to the capacitor current. First and second switched capacitor circuits are coupled to the first path. A fractional divider circuit is coupled to receive a clock signal to generate in response to an adjustable fractional divider ratio K a switched capacitor control signal that oscillates between first and second states to control the first and second switched capacitor circuits. The first and second switched capacitor circuits are coupled to be alternatingly charged by the capacitor current and discharged in response to each the switched capacitor control signal. An integrator coupled is to the second path to generate the ramp signal in response to the integrator current.
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公开(公告)号：US20160309106A1
公开(公告)日：2016-10-20
申请号：US14688260
申请日：2015-04-16
Applicant: OMNIVISION TECHNOLOGIES, INC.
Inventor： Liang Zuo , Zhiqiang Song , Liping Deng
CPC classification number: H04N5/378 , H04N5/357 , H04N5/3745
Abstract: A readout circuit for use in an image sensor includes a sense amplifier circuit coupled to a bitline to sense analog image data from a pixel cell of the image sensor. An analog to digital converter is coupled to the sense amplifier circuit to convert the analog image data to digital image data. A ramp generator circuit is coupled to generate a first ramp signal. The analog to digital converter is coupled to generate the digital image data in response to the analog image data and the first ramp signal. A first capacitive voltage divider is coupled to the ramp generator. The first capacitive voltage divider is coupled to reduce an output voltage swing of the first ramp signal coupled to be received by the analog to digital converter to reduce noise in the first ramp signal.
Abstract translation: 用于图像传感器的读出电路包括耦合到位线的读出放大器电路，以检测来自图像传感器的像素单元的模拟图像数据。 模数转换器耦合到读出放大器电路，以将模拟图像数据转换为数字图像数据。 斜坡发生器电路被耦合以产生第一斜坡信号。 模拟数字转换器被耦合以响应于模拟图像数据和第一斜坡信号而生成数字图像数据。 第一电容分压器耦合到斜坡发生器。 第一电容性分压器被耦合以减少耦合以由模数转换器接收的第一斜坡信号的输出电压摆幅，以减少第一斜坡信号中的噪声。
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Patent Agency Ranking
6.发明授权Image sensor power supply rejection ratio noise reduction through ramp generator 有权图像传感器电源抑制比通过斜坡发生器降噪公开(公告)号：US09380208B1
公开(公告)日：2016-06-28
申请号：US14685151
申请日：2015-04-13
Applicant: OMNIVISION TECHNOLOGIES, INC.
Inventor： Bi Yuan , Quifeng Jin , Liping Deng , Liang Zuo
CPC classification number: H04N5/23241 , H04N5/357 , H04N5/3577 , H04N5/378
Abstract: A ramp generator includes a supply voltage sampling circuit coupled to sample a black signal supply voltage during a black signal readout, and an image signal supply voltage of the pixel cell during an image signal readout of a pixel cell. A first integrator circuit receives a buffered reference voltage, and an output of the supply voltage sampling circuit. First and second switches are coupled between the first integrator circuit and a first capacitor to transfer a signal representative of a difference between the image signal supply voltage and the black signal supply voltage to the first capacitor. A second integrator circuit is coupled to the first capacitor to generate an output ramp signal coupled to be received by an analog to digital converter. A starting value of the output ramp signal is adjusted in response to the difference between the image signal and the black signal supply voltage.
Abstract translation: 斜坡发生器包括在黑色信号读出期间耦合以对黑色信号电源电压进行采样的电源电压采样电路，以及在像素单元的图像信号读出期间像素单元的图像信号供应电压。 第一积分器电路接收缓冲的参考电压和电源电压采样电路的输出。 第一和第二开关耦合在第一积分器电路和第一电容器之间，以将表示图像信号电源电压和黑色信号电源电压之间的差异的信号传送到第一电容器。 第二积分器电路耦合到第一电容器以产生耦合以由模数转换器接收的输出斜坡信号。 响应于图像信号和黑色信号电源电压之间的差异来调整输出斜坡信号的起始值。
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公开(公告)号：US20250047995A1
公开(公告)日：2025-02-06
申请号：US18363473
申请日：2023-08-01
Applicant: OMNIVISION TECHNOLOGIES, INC.
Inventor： Liang Zuo , Hiroaki Ebihara , Jing Jun Yi , Rui Wang , Satoshi Sakurai
IPC: H04N25/677 , H04N25/766 , H04N25/772
Abstract: An imaging system comprises a pixel array and readout circuitry coupled to the pixel array. The readout circuitry includes a ramp generator and a plurality of column unit cells, each comprising a column ramp buffer and a column comparator, and each column ramp buffer comprising an input node coupled to receive a ramp signal from the ramp generator, a transistor having a gate terminal coupled to the input node and a drain terminal coupled to a power line, an output node coupled between a source terminal of the transistor and the column comparator, and an alternating current (AC) coupling unit coupled between the input node and the transistor. The AC coupling unit comprises a capacitor coupled between the input node and the gate terminal of the transistor, and a reset switch coupled between the input node and the gate terminal of the transistor.
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公开(公告)号：US11431939B1
公开(公告)日：2022-08-30
申请号：US17217935
申请日：2021-03-30
Applicant: OMNIVISION TECHNOLOGIES, INC.
Inventor： Lihang Fan , Nijun Jiang , Liang Zuo , Yuedan Li , Min Qu
Abstract: A clock control circuit of an ADC includes a plurality of fractional divider circuits, each including a programmable integer divider coupled to receive an enable skew signal, a clock signal, and an output integer signal to divide down the clock signal by a factor responsive to the output integer signal to generate a fractional divider signal. A delta-sigma modulator is coupled to receive a fractional modulus signal, an input integer signal, and the fractional divider signal to generate the output integer signal, which is a varying signal each cycle and having a long term average DC value substantially equal to a fractional divider ratio K. An extended gain control circuit is coupled to receive the fractional divider signal from each of the fractional divider circuits to generate a plurality of ramp clock signals with adjustable frequencies to adjust a gain setting of a ramp generator of the ADC.
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公开(公告)号：US20220078365A1
公开(公告)日：2022-03-10
申请号：US17531465
申请日：2021-11-19
Applicant: OMNIVISION TECHNOLOGIES, INC.
Inventor： Chengcheng Xu , Rui Wang , Bi Yuan , Liang Zuo
IPC: H04N5/378 , H04N5/3745 , H04N5/374 , H04N5/376 , H04N5/369
Abstract: An image sensing device includes an image sensing circuit, a voltage supply grid, bitlines, and a control circuit. The image sensing circuit includes pixels arranged in rows and columns. Each one of the bitlines is coupled to a corresponding one of the columns. The voltage supply grid is coupled to the pixels. The control circuit is coupled to output at least a row select signal and a transfer signal to the rows. Each one of the rows is selectively coupled to the bitlines to selectively output image data signals in response to the row select signal and the transfer signal. Each one of the rows is further selectively coupled to the bitlines to selectively clamp the bitlines in response to the row select signal and the transfer signal. Each one of the rows is selectively decoupled from the bitlines in response to the row select signal.
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公开(公告)号：US20210176417A1
公开(公告)日：2021-06-10
申请号：US16708135
申请日：2019-12-09
Applicant: OMNIVISION TECHNOLOGIES, INC.
Inventor： Chengcheng Xu , Rui Wang , Bi Yuan , Liang Zuo
IPC: H04N5/378 , H04N5/3745
Abstract: An image sensing device includes an image sensing circuit, a voltage supply grid, bitlines, and a control circuit. The image sensing circuit includes pixels arranged in rows and columns. Each one of the bitlines is coupled to a corresponding one of the columns. The voltage supply grid is coupled to the pixels. The control circuit is coupled to output at least a row select signal and a transfer signal to the rows. Each one of the rows is selectively coupled to the bitlines to selectively output image data signals in response to the row select signal and the transfer signal. Each one of the rows is further selectively coupled to the bitlines to selectively clamp the bitlines in response to the row select signal and the transfer signal. Each one of the rows is selectively decoupled from the bitlines in response to the row select signal.
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