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    NON-VOLATILE MEMORY STRUCTURE EMPLOYING HIGH-K GATE DIELECTRIC AND METAL GATE
    52.
    发明申请
    NON-VOLATILE MEMORY STRUCTURE EMPLOYING HIGH-K GATE DIELECTRIC AND METAL GATE 有权
    使用高K门电介质和金属门的非易失性存储器结构

    公开(公告)号：US20140057426A1

    公开(公告)日：2014-02-27

    申请号：US14066119

    申请日：2013-10-29

    Applicant: International Business Machines Corporation

    Inventor： Nicolas Breil ,  Michael P. Chudzik ,  Rishikesh Krishnan ,  Siddarth A. Krishnan ,  Unoh Kwon

    IPC: H01L21/28 ,  H01L21/02

    CPC classification number: H01L21/28273 ,  H01L21/0228 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/823892 ,  H01L27/11546 ,  H01L29/42376 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/7881

    Abstract: A high dielectric constant (high-k) gate dielectric for a field effect transistor (FET) and a high-k tunnel dielectric for a non-volatile random access memory (NVRAM) device are simultaneously formed on a semiconductor substrate. A stack of at least one conductive material layer, a control gate dielectric layer, and a disposable material layer is subsequently deposited and lithographically patterned. A planarization dielectric layer is deposited and patterned, and disposable material portions are removed. A remaining portion of the control gate dielectric layer is preserved in the NVRAM device region, but is removed in the FET region. A conductive material is deposited in gate cavities to provide a control gate for the NVRAM device and a gate portion for the FET. Alternately, the control gate dielectric layer may replaced with a high-k control gate dielectric in the NVRAM device region.

    Abstract translation: 在半导体衬底上同时形成用于场效应晶体管（FET）的高介电常数（高k）栅极电介质和非易失性随机存取存储器（NVRAM）器件的高k隧道电介质。 随后沉积至少一个导电材料层，控制栅极电介质层和一次性材料层的堆叠并且被光刻图案化。 沉积并图案化平坦化介电层，并且去除一次性材料部分。 控制栅极电介质层的剩余部分保留在NVRAM器件区域中，但在FET区域中被去除。 导电材料沉积在栅极腔中以为NVRAM器件提供控制栅极和用于FET的栅极部分。 或者，控制栅介质层可以用NVRAM器件区域中的高k控制栅极电介质代替。

    Gate stack with tunable work function
    58.
    发明授权
    Gate stack with tunable work function 有权
    具有可调工作功能的门栈

    公开(公告)号：US09583400B1

    公开(公告)日：2017-02-28

    申请号：US14996563

    申请日：2016-01-15

    Applicant: International Business Machines Corporation

    Inventor： Ruqiang Bao ,  Siddarth A. Krishnan ,  Unoh Kwon ,  Vijay Narayanan

    IPC: H01L21/3205 ,  H01L21/4763 ,  H01L21/8238 ,  H01L21/28 ,  H01L29/66 ,  H01L29/49 ,  H01L27/092

    CPC classification number: H01L21/823842 ,  H01L21/28088 ,  H01L21/823821 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/4966 ,  H01L29/66545

    Abstract: A method for fabricating a gate stack of a semiconductor device comprising forming a first dielectric layer over a channel region of the device, forming a barrier layer over the first dielectric layer, forming a first gate metal layer over the barrier layer, forming a capping layer over the first gate metal layer, removing portions of the barrier layer, the first gate metal layer, and the capping layer to expose a portion of the first dielectric layer in a p-type field effect transistor (pFET) region of the gate stack, depositing a first nitride layer on exposed portions of the capping layer and the first dielectric layer, depositing a scavenging layer on the first nitride layer, depositing a second nitride layer on the scavenging layer, and depositing a gate electrode material on the second nitride layer.

    Abstract translation: 一种用于制造半导体器件的栅极堆叠的方法，包括在器件的沟道区上形成第一介电层，在第一介电层上形成阻挡层，在阻挡层上形成第一栅极金属层，形成覆盖层 在第一栅极金属层之上，去除阻挡层，第一栅极金属层和覆盖层的部分，以暴露栅极堆叠的p型场效应晶体管（pFET）区域中的第一介电层的一部分， 在所述覆盖层和所述第一介电层的暴露部分上沉积第一氮化物层，在所述第一氮化物层上沉积清除层，在所述扫气层上沉积第二氮化物层，以及在所述第二氮化物层上沉积栅电极材料。

    Forming a semiconductor structure for reduced negative bias temperature instability
    59.
    发明授权
    Forming a semiconductor structure for reduced negative bias temperature instability 有权
    形成半导体结构，减少负偏温度不稳定性

    公开(公告)号：US09502307B1

    公开(公告)日：2016-11-22

    申请号：US14947350

    申请日：2015-11-20

    Applicant: International Business Machines Corporation

    Inventor： Ruqiang Bao ,  Siddarth A. Krishnan

    IPC: H01L21/8238 ,  H01L29/66 ,  H01L29/49 ,  H01L29/51 ,  H01L27/092

    CPC classification number: H01L21/823857 ,  H01L21/28088 ,  H01L21/28176 ,  H01L21/28556 ,  H01L21/3003 ,  H01L21/3115 ,  H01L21/3215 ,  H01L21/823828 ,  H01L21/823842 ,  H01L21/82385 ,  H01L27/092 ,  H01L29/42364 ,  H01L29/42372 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517

    Abstract: An approach to forming a semiconductor structure with improved negative bias temperature instability includes forming an interfacial layer on a semiconductor substrate with an nFET and a pFET. The approach includes depositing a gate dielectric layer on the interfacial layer. Additionally, the approach includes an nFET work function metal layer deposited on the interfacial layer. Additionally, the approach includes removing the nFET work function metal from an area above the pFET and depositing a pFET work function metal layer on a portion of the exposed gate dielectric layer where the portion of the exposed gate dielectric layer is over the pFET. Furthermore, the approach includes depositing a gate metal on the pFET work function metal layer where the gate metal is deposited in an environment with a fluorine containing gas followed by an anneal in a reducing environment.

    Abstract translation: 形成具有改善的负偏压温度不稳定性的半导体结构的方法包括在nFET和pFET的半导体衬底上形成界面层。 该方法包括在界面层上沉积栅极电介质层。 此外，该方法包括沉积在界面层上的nFET功函数金属层。 另外，该方法包括从pFET上方的区域去除nFET功函数金属，并且将pFET功函数金属层沉积在暴露的栅极介电层的暴露的栅极介电层的一部分在pFET上方的部分上。 此外，该方法包括在pFET功函数金属层上沉积栅极金属，其中栅极金属在具有含氟气体的环境中沉积，然后在还原环境中进行退火。

    CONSTRAINED NANOSECOND LASER ANNEAL OF METAL INTERCONNECT STRUCTURES
    60.
    发明申请
    CONSTRAINED NANOSECOND LASER ANNEAL OF METAL INTERCONNECT STRUCTURES 有权
    金属互连结构的约束纳米激光雷达

    公开(公告)号：US20160086849A1

    公开(公告)日：2016-03-24

    申请号：US14490792

    申请日：2014-09-19

    Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES Inc.

    Inventor： Oleg Gluschenkov ,  Siddarth A. Krishnan ,  Joyeeta Nag ,  Andrew H. Simon ,  Shishir Ray

    IPC: H01L21/768

    CPC classification number: H01L21/76894 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76867 ,  H01L21/76883 ,  H01L23/53228 ,  H01L23/53233 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/01029 ,  H01L2924/00

    Abstract: In-situ melting and crystallization of sealed cooper wires can be performed by means of laser annealing for a duration of nanoseconds. The intensity of the laser irradiation is selected such that molten copper wets interconnect interfaces, thereby forming an interfacial bonding arrangement that increases specular scattering of electrons. Nanosecond-scale temperature quenching preserves the formed interfacial bonding. At the same time, the fast crystallization process of sealed copper interconnects results in large copper grains, typically larger than 80 nm in lateral dimensions, on average. A typical duration of the annealing process is from about 10's to about 100's of nanoseconds. There is no degradation to interlayer low-k dielectric material despite the high anneal temperature due to ultra short duration that prevents collective motion of atoms within the dielectric material.

    Abstract translation: 密封铜线的原位熔融和结晶可以通过激光退火进行纳秒的持续时间。 选择激光照射的强度，使得熔融铜浸润互连界面，从而形成增加电子的镜面散射的界面结合装置。 纳秒级温度淬火保持形成的界面结合。 同时，密封铜互连的快速结晶过程平均导致大的铜晶粒，通常大于80nm的横向尺寸。 退火过程的典型持续时间为约10秒至约100秒的纳秒。 尽管由于超短时间的高退火温度，层间低k介电材料没有劣化，从而防止原子在电介质材料内的集体运动。

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