公开(公告)号：US08394688B2

公开(公告)日：2013-03-12

申请号：US13169129

申请日：2011-06-27

Applicant: Chien-Liang Lin ,  Ying-Wei Yen ,  Yu-Ren Wang

Inventor： Chien-Liang Lin ,  Ying-Wei Yen ,  Yu-Ren Wang

IPC: H01L21/336 ,  H01L21/8234

CPC classification number: H01L29/7834 ,  H01L21/28035 ,  H01L21/28247 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636

Abstract: A repair layer forming process includes the following steps. Firstly, a substrate is provided, and a gate structure is formed on the substrate, wherein the gate structure at least includes a gate dielectric layer and a gate conductor layer. Then, a nitridation process is performed to form a nitrogen-containing superficial layer on a sidewall of the gate structure. Then, a thermal oxidation process is performed to convert the nitrogen-containing superficial layer into a repair layer. Moreover, a metal-oxide-semiconductor transistor includes a substrate, a gate dielectric layer, a gate conductor layer and a repair layer. The gate dielectric layer is formed on the substrate. The gate conductor layer is formed on the gate dielectric layer. The repair layer is at least partially formed on a sidewall of the gate conductor layer.

Abstract translation: 修复层形成方法包括以下步骤。 首先，提供衬底，并且在衬底上形成栅极结构，其中栅极结构至少包括栅极介电层和栅极导体层。 然后，进行氮化处理以在栅极结构的侧壁上形成含氮表面层。 然后，进行热氧化处理以将含氮表层转化为修复层。 此外，金属氧化物半导体晶体管包括基板，栅极电介质层，栅极导体层和修复层。 栅极电介质层形成在基板上。 栅极导体层形成在栅极电介质层上。 修复层至少部分地形成在栅极导体层的侧壁上。

公开(公告)号：US20120326162A1

公开(公告)日：2012-12-27

申请号：US13169129

申请日：2011-06-27

Applicant: Chien-Liang LIN ,  Ying-Wei Yen ,  Yu-Ren Wang

Inventor： Chien-Liang LIN ,  Ying-Wei Yen ,  Yu-Ren Wang

IPC: H01L29/12 ,  H01L21/28 ,  H01L29/78 ,  B82Y30/00 ,  B82Y40/00

CPC classification number: H01L29/7834 ,  H01L21/28035 ,  H01L21/28247 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636

Abstract: A repair layer forming process includes the following steps. Firstly, a substrate is provided, and a gate structure is formed on the substrate, wherein the gate structure at least includes a gate dielectric layer and a gate conductor layer. Then, a nitridation process is performed to form a nitrogen-containing superficial layer on a sidewall of the gate structure. Then, a thermal oxidation process is performed to convert the nitrogen-containing superficial layer into a repair layer. Moreover, a metal-oxide-semiconductor transistor includes a substrate, a gate dielectric layer, a gate conductor layer and a repair layer. The gate dielectric layer is formed on the substrate. The gate conductor layer is formed on the gate dielectric layer. The repair layer is at least partially formed on a sidewall of the gate conductor layer.

Abstract translation: 修复层形成方法包括以下步骤。 首先，提供衬底，并且在衬底上形成栅极结构，其中栅极结构至少包括栅极介电层和栅极导体层。 然后，进行氮化处理以在栅极结构的侧壁上形成含氮表面层。 然后，进行热氧化处理以将含氮表层转化为修复层。 此外，金属氧化物半导体晶体管包括基板，栅极电介质层，栅极导体层和修复层。 栅极电介质层形成在基板上。 栅极导体层形成在栅极电介质层上。 修复层至少部分地形成在栅极导体层的侧壁上。

公开(公告)号：US20120264267A1

公开(公告)日：2012-10-18

申请号：US13084564

申请日：2011-04-12

Applicant: Tsuo-Wen Lu ,  Gin-Chen Huang ,  Shao-Wei Wang ,  Yu-Ren Wang ,  Ya-Chi Cheng

Inventor： Tsuo-Wen Lu ,  Gin-Chen Huang ,  Shao-Wei Wang ,  Yu-Ren Wang ,  Ya-Chi Cheng

IPC: H01L21/336

CPC classification number: H01L29/66636 ,  H01L29/165 ,  H01L29/6659 ,  H01L29/7834

Abstract: A method of fabricating a MOS transistor includes the steps of: providing a substrate; forming a gate structure on the substrate; forming a first spacer on the sidewall of the gate structure and forming at least a recess within the substrate next to the first spacer; performing an oxygen-containing process to form an oxygen-containing layer on the surface of the recess; performing a cleaning process to remove the oxygen-containing layer; performing an epitaxial process to form an epitaxial layer in the recess; and removing the first spacer.

Abstract translation: 制造MOS晶体管的方法包括以下步骤：提供衬底; 在基板上形成栅极结构; 在所述栅极结构的侧壁上形成第一间隔物，并在所述基板内至少形成一个与所述第一间隔物相邻的凹槽; 在所述凹部的表面上进行含氧处理以形成含氧层; 进行清洗处理以除去含氧层; 执行外延工艺以在所述凹部中形成外延层; 并移除第一间隔物。

公开(公告)号：US20120202328A1

公开(公告)日：2012-08-09

申请号：US13450476

申请日：2012-04-19

Applicant: Tsuo-Wen Lu ,  Tsai-Fu Hsiao ,  Yu-Ren Wang ,  Shu-Yen Chan

Inventor： Tsuo-Wen Lu ,  Tsai-Fu Hsiao ,  Yu-Ren Wang ,  Shu-Yen Chan

IPC: H01L21/336

CPC classification number: H01L29/66636 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/7834

Abstract: The invention discloses a method for fabricating a MOS transistor. A substrate having thereon a gate structure is provided. A silicon nitride layer is deposited on the gate structure. A dry etching process is then performed to define a silicon nitride spacer on each sidewall of the gate structure and a recess in a source/drain region on each side of the gate structure. A transitional layer covering the gate structure and the recess is deposited. A pre-epitaxial clean process is performed to remove the transitional layer. The substrate is subjected to a pre-bake process. An epitaxial growth process is performed to grow an embedded SiGe layer in the recess. The disposable silicon nitride spacer is removed.

公开(公告)号：US08232605B2

公开(公告)日：2012-07-31

申请号：US12337541

申请日：2008-12-17

Applicant: Chien-Liang Lin ,  Yu-Ren Wang ,  Wu-Chun Kao ,  Ying-Hsuan Li ,  Ying-Wei Yen ,  Shu-Yen Chan

Inventor： Chien-Liang Lin ,  Yu-Ren Wang ,  Wu-Chun Kao ,  Ying-Hsuan Li ,  Ying-Wei Yen ,  Shu-Yen Chan

IPC: H01L29/76

CPC classification number: H01L21/823807 ,  H01L21/823857

Abstract: The present invention relates to a method for gate leakage reduction and Vt shift control, in which a first ion implantation is performed on PMOS region and NMOS region of a substrate to implant fluorine ions, carbon ions, or both in the gate dielectric or the semiconductor substrate, and a second ion implantation is performed only on the NMOS region of the substrate to implant fluorine ions, carbon ions, or both in the gate dielectric or the semiconductor substrate in the NMOS region, with the PMOS region being covered by a mask layer. Thus, the doping concentrations obtained by the PMOS region and the NMOS region are different to compensate the side effect caused by the different equivalent oxide thickness and to avoid the Vt shift.

Abstract translation: 本发明涉及一种用于栅极泄漏减小和Vt移位控制的方法，其中在衬底的PMOS区域和NMOS区域上执行第一离子注入以在栅极电介质或半导体中注入氟离子，碳离子或两者 衬底，并且仅在衬底的NMOS区域上执行第二离子注入，以在NMOS区域中的栅极电介质或半导体衬底中注入氟离子，碳离子或两者，其中PMOS区被掩模层覆盖 。 因此，由PMOS区域和NMOS区域获得的掺杂浓度不同，以补偿不同等效氧化物厚度引起的副作用并避免Vt偏移。

公开(公告)号：US20050215019A1

公开(公告)日：2005-09-29

申请号：US10812433

申请日：2004-03-29

Applicant: Yu-Ren Wang ,  Ying Yen ,  Tony Liu

Inventor： Yu-Ren Wang ,  Ying Yen ,  Tony Liu

IPC: H01L21/00 ,  H01L21/336 ,  H01L21/84 ,  H01L29/78

CPC classification number: H01L29/6659 ,  H01L29/6656 ,  H01L29/7833

Abstract: A method of manufacturing a metal-oxide-semiconductor transistor is provided. A substrate having a gate structure thereon is provided. A source/drain extension region is formed in the substrate on each side of the gate structure. Thereafter, a carbon-containing material layer is formed over the substrate and then the carbon-containing material layer is etched back to form spacers on the sidewalls of the gate structure. Finally, a source/drain region is formed in the substrate on each side of the spacer-coated gate structure.

Abstract translation: 提供一种制造金属氧化物半导体晶体管的方法。 提供其上具有栅极结构的衬底。 在栅极结构的每一侧的衬底中形成源极/漏极延伸区域。 此后，在衬底上形成含碳材料层，然后将含碳材料层回蚀刻以在栅极结构的侧壁上形成间隔物。 最后，在间隔物涂覆的栅极结构的每一侧上的衬底中形成源/漏区。

公开(公告)号：US06943085B2

公开(公告)日：2005-09-13

申请号：US10667229

申请日：2003-09-17

Applicant: Yu-Ren Wang ,  Chin-Cheng Chien ,  Hsiang-Ying Wang ,  Neng-Hui Yang

Inventor： Yu-Ren Wang ,  Chin-Cheng Chien ,  Hsiang-Ying Wang ,  Neng-Hui Yang

IPC: H01L21/265 ,  H01L21/336

CPC classification number: H01L29/6659 ,  H01L21/26513 ,  H01L29/6656 ,  H01L29/66666

Abstract: A method of manufacturing a MOS transistor is provided. A substrate having a gate structure thereon is provided. A first spacer is formed on the sidewall of the gate structure. A pre-amorphization implantation is carried out to amorphize a portion of the substrate. A doped source/drain extension region is formed in the substrate on each side of the first spacer. A second spacer is formed on the sidewall of the first spacer. A doped source/drain region is formed in the substrate on each side of the second spacer and then a pre-annealing operation is performed. Thereafter, a solid phase epitaxial process is carried out to re-crystallize the amorphized portion of the substrate and activate the doped source/drain extension region and the doped source/drain region to form a source/drain terminal. Finally, a post-annealing operation is performed.

公开(公告)号：US06893909B2

公开(公告)日：2005-05-17

申请号：US10681768

申请日：2003-10-07

Applicant: Yu-Ren Wang ,  Chun-Yi Lee ,  Yu-Kun Chen ,  Neng-Hui Yang

Inventor： Yu-Ren Wang ,  Chun-Yi Lee ,  Yu-Kun Chen ,  Neng-Hui Yang

IPC: H01L21/00 ,  H01L21/265 ,  H01L21/28 ,  H01L21/336 ,  H01L29/78

CPC classification number: H01L29/6659 ,  H01L21/265 ,  H01L21/28035 ,  H01L29/6656 ,  H01L29/7833

Abstract: A method of manufacturing a MOS transistor is provided. A gate insulation layer and a conductive layer are sequentially formed over a substrate. A pre-amorphization implantation is carried out to amorphize the conductive layer. The conductive layer and the gate insulation layer are patterned to form a gate structure. A first spacer is formed on the sidewall of the gate structure. A second pre-amorphization implantation is carried out to amorphize a portion of the substrate. A doped source/drain extension region is formed in the substrate on each side of the first spacer. A second spacer is formed on the sidewall of the first spacer and then a doped source/drain region is formed in the substrate on each side of the second spacer. A solid phase epitaxial process is carried out to convert the doped source/drain extension region and the doped source/drain region into a source/drain terminal. In the pre-amorphization implantations, dopants having an ionic radius greater than the germanium ion are used.

Abstract translation: 提供一种制造MOS晶体管的方法。 栅极绝缘层和导电层依次形成在衬底上。 进行前非晶化注入以使导电层非晶化。 将导电层和栅极绝缘层图案化以形成栅极结构。 在栅极结构的侧壁上形成第一间隔物。 进行第二次非晶化植入以使基板的一部分非晶化。 在第一间隔物的每一侧上的衬底中形成掺杂的源极/漏极延伸区域。 在第一间隔物的侧壁上形成第二间隔物，然后在第二间隔物的每一侧上的衬底中形成掺杂源/漏区。 进行固相外延处理以将掺杂的源极/漏极延伸区域和掺杂的源极/漏极区域转换成源极/漏极端子。 在前非晶化注入中，使用离子半径大于锗离子的掺杂剂。

公开(公告)号：US20050074931A1

公开(公告)日：2005-04-07

申请号：US10681768

申请日：2003-10-07

Applicant: Yu-Ren Wang ,  Chun-Yi Lee ,  Yu-Kun Chen ,  Neng-Hui Yang

Inventor： Yu-Ren Wang ,  Chun-Yi Lee ,  Yu-Kun Chen ,  Neng-Hui Yang

IPC: H01L21/00 ,  H01L21/265 ,  H01L21/28 ,  H01L21/336 ,  H01L29/78

CPC classification number: H01L29/6659 ,  H01L21/265 ,  H01L21/28035 ,  H01L29/6656 ,  H01L29/7833

Abstract: A method of manufacturing a MOS transistor is provided. A gate insulation layer and a conductive layer are sequentially formed over a substrate. A pre-amorphization implantation is carried out to amorphize the conductive layer. The conductive layer and the gate insulation layer are patterned to form a gate structure. A first spacer is formed on the sidewall of the gate structure. A second pre-amorphization implantation is carried out to amorphize a portion of the substrate. A doped source/drain extension region is formed in the substrate on each side of the first spacer. A second spacer is formed on the sidewall of the first spacer and then a doped source/drain region is formed in the substrate on each side of the second spacer. A solid phase epitaxial process is carried out to convert the doped source/drain extension region and the doped source/drain region into a source/drain terminal. In the pre-amorphization implantations, dopants having an ionic radius greater than the germanium ion are used.

Abstract translation: 提供一种制造MOS晶体管的方法。 栅极绝缘层和导电层依次形成在衬底上。 进行前非晶化注入以使导电层非晶化。 将导电层和栅极绝缘层图案化以形成栅极结构。 在栅极结构的侧壁上形成第一间隔物。 进行第二次非晶化植入以使基板的一部分非晶化。 在第一间隔物的每一侧上的衬底中形成掺杂的源极/漏极延伸区域。 在第一间隔物的侧壁上形成第二间隔物，然后在第二间隔物的每一侧上的衬底中形成掺杂源/漏区。 进行固相外延处理以将掺杂的源极/漏极延伸区域和掺杂的源极/漏极区域转换成源极/漏极端子。 在前非晶化注入中，使用离子半径大于锗离子的掺杂剂。

公开(公告)号：US20050054173A1

公开(公告)日：2005-03-10

申请号：US10667229

申请日：2003-09-17

Applicant: Yu-Ren Wang ,  Chin-Cheng Chien ,  Hsiang-Ying Wang ,  Neng-Hui Yang

Inventor： Yu-Ren Wang ,  Chin-Cheng Chien ,  Hsiang-Ying Wang ,  Neng-Hui Yang

IPC: H01L21/265 ,  H01L21/336 ,  H01L21/331

CPC classification number: H01L29/6659 ,  H01L21/26513 ,  H01L29/6656 ,  H01L29/66666

Abstract: A method of manufacturing a MOS transistor is provided. A substrate having a gate structure thereon is provided. A first spacer is formed on the sidewall of the gate structure. A pre-amorphization implantation is carried out to amorphize a portion of the substrate. A doped source/drain extension region is formed in the substrate on each side of the first spacer. A second spacer is formed on the sidewall of the first spacer. A doped source/drain region is formed in the substrate on each side of the second spacer and then a pre-annealing operation is performed. Thereafter, a solid phase epitaxial process is carried out to re-crystallize the amorphized portion of the substrate and activate the doped source/drain extension region and the doped source/drain region to form a source/drain terminal. Finally, a post-annealing operation is performed.

Abstract translation: 提供一种制造MOS晶体管的方法。 提供其上具有栅极结构的衬底。 在栅极结构的侧壁上形成第一间隔物。 进行预非晶化注入以使基板的一部分非晶化。 在第一间隔物的每一侧上的衬底中形成掺杂的源极/漏极延伸区域。 第二间隔件形成在第一间隔件的侧壁上。 在第二间隔物的每一侧上的衬底中形成掺杂的源/漏区，然后进行预退火操作。 此后，进行固相外延处理以重新结晶衬底的非晶化部分并激活掺杂的源极/漏极延伸区域和掺杂源极/漏极区域以形成源极/漏极端子。 最后，执行后退火操作。