公开(公告)号：US08232605B2

公开(公告)日：2012-07-31

申请号：US12337541

申请日：2008-12-17

Applicant: Chien-Liang Lin ,  Yu-Ren Wang ,  Wu-Chun Kao ,  Ying-Hsuan Li ,  Ying-Wei Yen ,  Shu-Yen Chan

Inventor： Chien-Liang Lin ,  Yu-Ren Wang ,  Wu-Chun Kao ,  Ying-Hsuan Li ,  Ying-Wei Yen ,  Shu-Yen Chan

IPC: H01L29/76

CPC classification number: H01L21/823807 ,  H01L21/823857

Abstract: The present invention relates to a method for gate leakage reduction and Vt shift control, in which a first ion implantation is performed on PMOS region and NMOS region of a substrate to implant fluorine ions, carbon ions, or both in the gate dielectric or the semiconductor substrate, and a second ion implantation is performed only on the NMOS region of the substrate to implant fluorine ions, carbon ions, or both in the gate dielectric or the semiconductor substrate in the NMOS region, with the PMOS region being covered by a mask layer. Thus, the doping concentrations obtained by the PMOS region and the NMOS region are different to compensate the side effect caused by the different equivalent oxide thickness and to avoid the Vt shift.

Abstract translation: 本发明涉及一种用于栅极泄漏减小和Vt移位控制的方法，其中在衬底的PMOS区域和NMOS区域上执行第一离子注入以在栅极电介质或半导体中注入氟离子，碳离子或两者 衬底，并且仅在衬底的NMOS区域上执行第二离子注入，以在NMOS区域中的栅极电介质或半导体衬底中注入氟离子，碳离子或两者，其中PMOS区被掩模层覆盖 。 因此，由PMOS区域和NMOS区域获得的掺杂浓度不同，以补偿不同等效氧化物厚度引起的副作用并避免Vt偏移。

公开(公告)号：US20100148271A1

公开(公告)日：2010-06-17

申请号：US12337541

申请日：2008-12-17

Applicant: Chien-Liang Lin ,  Yu-Ren Wang ,  Wu-Chun Kao ,  Ying-Hsuan Li ,  Ying-Wei Yen ,  Shu-Yen Chan

Inventor： Chien-Liang Lin ,  Yu-Ren Wang ,  Wu-Chun Kao ,  Ying-Hsuan Li ,  Ying-Wei Yen ,  Shu-Yen Chan

IPC: H01L27/092 ,  H01L21/426

CPC classification number: H01L21/823807 ,  H01L21/823857

Abstract: The present invention relates to a method for gate leakage reduction and Vt shift control, in which a first ion implantation is performed on PMOS region and NMOS region of a substrate to implant fluorine ions, carbon ions, or both in the gate dielectric or the semiconductor substrate, and a second ion implantation is performed only on the NMOS region of the substrate to implant fluorine ions, carbon ions, or both in the gate dielectric or the semiconductor substrate in the NMOS region, with the PMOS region being covered by a mask layer. Thus, the doping concentrations obtained by the PMOS region and the NMOS region are different to compensate the side effect caused by the different equivalent oxide thickness and to avoid the Vt shift.

Abstract translation: 本发明涉及一种用于栅极泄漏减小和Vt移位控制的方法，其中在衬底的PMOS区域和NMOS区域上执行第一离子注入以在栅极电介质或半导体中注入氟离子，碳离子或两者 衬底，并且仅在衬底的NMOS区域上执行第二离子注入，以在NMOS区域中的栅极电介质或半导体衬底中注入氟离子，碳离子或两者，其中PMOS区被掩模层覆盖 。 因此，由PMOS区域和NMOS区域获得的掺杂浓度不同，以补偿不同等效氧化物厚度引起的副作用并避免Vt偏移。