公开(公告)号：US5239633A

公开(公告)日：1993-08-24

申请号：US497375

申请日：1990-05-04

申请人： Fumihiko Terayama ,  Yuichi Saitou ,  Toyohiko Yoshida

发明人： Fumihiko Terayama ,  Yuichi Saitou ,  Toyohiko Yoshida

IPC分类号： G06F9/38

CPC分类号： G06F9/3824

摘要： A data processor which comprises a pipeline processing mechanism for executing memory indirect addressing and register indirect addressing in an address calculation stage, checks whether or not an instruction writes an operand to a memory or register, makes each stage of the pipeline mechanism hold reservation information thereof in sequence, thereby reduces the frequency of stops of pipeline processing caused by processing of operand address calculation of the following instruction attending on a writing of the operand of the preceding instruction to a memory or register, so that data processing can be execute at a higher efficiency.

摘要翻译： 一种数据处理器，包括用于在地址计算阶段执行存储器间接寻址和寄存器间接寻址的流水线处理机构，检查指令是否将操作数写入存储器或寄存器，使流水线机构的每一级保持其预留信息 从而降低了由于将前一条指令的操作数写入到存储器或寄存器中的下列指令的操作数地址计算处理引起的流水线处理停止频率，从而数据处理可以在较高的值 效率。

公开(公告)号：US5193156A

公开(公告)日：1993-03-09

申请号：US312554

申请日：1989-02-17

申请人： Toyohiko Yoshida ,  Masahito Matuo

发明人： Toyohiko Yoshida ,  Masahito Matuo

IPC分类号： G06F9/38

CPC分类号： G06F9/38

摘要： The data processor of this invention is provided with a multi-stage pipeline processing mechanism which predicts the probability of the branch instruction branching at the instruction decoding stage. The mechanism also detects exceptions at pre-branching and transmits information about a detected exception to the instruction execution stage. If, at the execution stage, it is determined that the branch prediction was incorrect, exception processing is not started. If, at the execution stage, it is determined that the branch prediction was correct, exception processing is started. In this way it is possible to reduce disturbances in pipeline processing for many branch instructions.

摘要翻译： 本发明的数据处理器设置有多级流水线处理机构，其预测在指令解码级分支的分支指令的概率。 该机制还检测分支前的异常，并将关于检测到的异常的信息发送到指令执行阶段。 如果在执行阶段确定分支预测不正确，则不开始异常处理。 如果在执行阶段确定分支预测是正确的，则开始异常处理。 以这种方式，可以减少许多分支指令的流水线处理中的干扰。

公开(公告)号：US5140684A

公开(公告)日：1992-08-18

申请号：US663282

申请日：1991-02-28

申请人： Ken Sakamura ,  Toyohiko Yoshida

发明人： Ken Sakamura ,  Toyohiko Yoshida

IPC分类号： G06F12/14

CPC分类号： G06F12/1491

摘要： The data processor related to the invention accesses memory with an address value which is expressed by signed binary notation expressed by twos compliment, is so constructed that the negative address value having maximum absolute value and the positive address value having the same are not wrapped around each other, is provided with hardware which signed extends the address values expressed by relatively small bit number, and is so constructed that the user area and the supervisor area are separated from each other in accordance with the positiveness and the negativeness of address value, so that the positive and negative address space are allowed to optionally be extended in the direction of the greater absolute value without being split, and extending process of address value is easy, furthermore, the user area and the supervisor area can be judged merely by means of the signed bit denoting either the positiveness or the negativeness, to thereby violation of the access right in the supervisor area under the user mode being able to easily be detected.

摘要翻译： 与本发明相关的数据处理器以由二进制表示的有符号二进制符号表示的地址值访问存储器被构造成使得具有最大绝对值的负地址值和具有相同值的正地址值不被包围在每个 另一方面，具有签名的硬件扩展了由相对小的比特数表示的地址值，并且被构造成使得用户区域和主管区域根据地址值的积极性和否定性而彼此分离，使得 允许正，负地址空间在绝对值较大的方向上被扩展，而不会被拆分，并且地址值的扩展处理容易，此外，用户区域和主管区域只能通过 签署的位表示积极性或否定性，从而违反了访问权限 用户模式下的主管区域能够容易地被检测。

公开(公告)号：US5132898A

公开(公告)日：1992-07-21

申请号：US631197

申请日：1990-12-20

申请人： Ken Sakamura ,  Toyohiko Yoshida

发明人： Ken Sakamura ,  Toyohiko Yoshida

IPC分类号： G06F5/00 ,  G06F7/76 ,  G06F13/40

CPC分类号： G06F7/768 ,  G06F13/4013 ,  G06F5/00

摘要： A data processor that executes arithmetic operations between first and second binary numbers, stored in different registers, of different lengths, with the first number having a byte-length smaller than the register, and the second number having a byte-length equal to the register, by storing the first number so that its lower order bit is justified with the lower order bit of the second number. Additionally, data having different bit and byte polarities are processed by reversing the bit and byte order of the data as required.

摘要翻译： 一种数据处理器，其执行存储在不同长度的不同寄存器中的第一和第二二进制数之间的算术运算，第一个数字的字节长度小于寄存器，第二个数字具有等于寄存器的字节长度 ，通过存储第一个数字，使得它的低阶位与第二个数字的低位位对齐。 另外，通过根据需要反转数据的位和字节顺序来处理具有不同位和字节极性的数据。

公开(公告)号：US4858104A

公开(公告)日：1989-08-15

申请号：US143547

申请日：1988-01-13

申请人： Masahito Matsuo ,  Toyohiko Yoshida

发明人： Masahito Matsuo ,  Toyohiko Yoshida

IPC分类号： G06F9/38

CPC分类号： G06F9/3844

摘要： A branch prediction for predicting, prior to executing a given branch instruction, whether the branch condition of the given branch instruction will be established, utilizes an address of an instruction that precedes the given branch instruction to access the branch prediction information for the given branch instruction from a branch prediction table.

摘要翻译： 一种分支预测，用于在执行给定的分支指令之前，预测给定分支指令的分支条件是否将被建立，利用在给定分支指令之前的指令的地址来访问给定分支指令的分支预测信息 从分支预测表。

公开(公告)号：US4755968A

公开(公告)日：1988-07-05

申请号：US875447

申请日：1986-06-17

申请人： Toyohiko Yoshida ,  Yoshihiro Seguchi

发明人： Toyohiko Yoshida ,  Yoshihiro Seguchi

IPC分类号： G06F12/12 ,  G11C7/00 ,  G11C13/00

CPC分类号： G11C7/00

摘要： A buffer memory device is formed of: a plurality of memory blocks each comprising a register and a comparator for comparing the content of said register and the input data. A control circuit controls the shift of the data of said registers in such a manner that only the contents of said registers from the first memory block to a desired memory block are shifted.

摘要翻译： 缓冲存储器件由以下部件组成：多个存储器块，每个存储器块包括用于比较所述寄存器的内容和输入数据的寄存器和比较器。 控制电路以这样的方式控制所述寄存器的数据的移位，使得仅将所述寄存器的内容从第一存储器块移动到期望的存储器块。

公开(公告)号：US20100011191A1

公开(公告)日：2010-01-14

申请号：US12564397

申请日：2009-09-22

申请人： Toyohiko YOSHIDA

发明人： Toyohiko YOSHIDA

IPC分类号： G06F9/30

CPC分类号： G06F9/30174

摘要： A data processing device includes a processor core, and a memory interface portion arranged between the processor core and an external memory mapped into a predetermined external memory space. The memory interface portion includes a fetch circuit for receiving an address value for access to the external memory space from the processor core, and fetching the data at the address in the external memory, a translator for translating the normative instruction fetched from the external memory into the native instruction, and a select circuit for selectively applying the data read from the external memory space and the instruction prepared by translating the instruction read from the external memory space by the translator to the processor core depending on whether the address value for the access to the external memory space is in a predetermined region or not.

摘要翻译： 数据处理装置包括处理器核心和布置在处理器核心和映射到预定外部存储器空间的外部存储器之间的存储器接口部分。 存储器接口部分包括一个提取电路，用于从处理器核心接收用于访问外部存储器空间的地址值，并且在外部存储器中的地址处获取数据;翻译器，用于将从外部存储器取出的标准化指令转换成 本地指令和用于选择性地应用从外部存储器空间读取的数据的选择电路以及通过将由翻译器从外部存储器空间读取的指令转换为处理器核心而准备的指令，这取决于访问的地址值 外部存储器空间处于预定区域。

公开(公告)号：US20080133887A1

公开(公告)日：2008-06-05

申请号：US11987704

申请日：2007-12-04

申请人： Toyohiko Yoshida ,  Akira Yamada ,  Hisakazu Sato

发明人： Toyohiko Yoshida ,  Akira Yamada ,  Hisakazu Sato

IPC分类号： G06F9/38

CPC分类号： G06F9/3814 ,  G06F7/5443 ,  G06F9/3802 ,  G06F9/381 ,  G06F9/3822 ,  G06F9/3875

摘要： When fetching an instruction from a plurality of memory banks, a first pipeline cycle corresponding to selection of a memory bank and a second pipeline cycle corresponding to instruction readout are generated to carry out a pipeline process. Only the selected memory bank can be precharged to allow reduction of power consumption. Since the first and second pipeline cycles are effected in parallel, the throughput of the instruction memory can be improved.

公开(公告)号：US06851045B2

公开(公告)日：2005-02-01

申请号：US09116260

申请日：1998-07-16

申请人： Edgar Holmann ,  Toyohiko Yoshida

发明人： Edgar Holmann ,  Toyohiko Yoshida

IPC分类号： G06F9/30 ,  G06F9/318 ,  G06F9/32 ,  G06F9/38 ,  G06F13/00

CPC分类号： G06F9/30192 ,  G06F9/30058 ,  G06F9/30145 ,  G06F9/30167 ,  G06F9/3842

摘要： A microprocessor including an instruction decoder for decoding a branch instruction to output a decoded result, a program counter, and a program counter controller for controlling the program counter on the basis of the decoded result. The program counter controller includes a first register for storing a first program counter value output from the instruction decoder. The program counter controller detects a coincidence of the first program counter value stored in the first register with a value of the program counter to set a second program counter value indicating a branch target of the branch instruction into the program counter.

摘要翻译： 一种微处理器，包括用于解码分支指令以输出解码结果的指令解码器，程序计数器和用于根据解码结果控制程序计数器的程序计数器控制器。 程序计数器控制器包括用于存储从指令译码器输出的第一程序计数值的第一寄存器。 程序计数器控制器检测存储在第一寄存器中的第一程序计数器值与程序计数器的值的一致，以将指示转移指令的分支目标的第二程序计数器值设置到程序计数器中。

公开(公告)号：US06792045B2

公开(公告)日：2004-09-14

申请号：US09769415

申请日：2001-01-26

申请人： Tetsuya Matsumura ,  Toyohiko Yoshida

发明人： Tetsuya Matsumura ,  Toyohiko Yoshida

IPC分类号： H04N712

CPC分类号： H04N19/40

摘要： An MPEG2 decoder portion decodes an input bit stream and outputs a digital decoded image while extracting coding information and supplying the same to a control portion. An MPEG2 encoder portion re-encodes the digital decoded image output from the MPEG2 decoder portion. Coding information supplied from the control portion is reflected on a coding parameter in re-encoding. Transcoding between the MPEG2 standard and the DV standard can also be executed by arranging a decoder or an encoder corresponding to the DV standard in place of either the MPEG2 decoder portion or the MPEG2 encoder portion.

摘要翻译： MPEG2解码器部分解码输入比特流并输出数字解码图像，同时提取编码信息并将其提供给控制部分。 MPEG2编码器部分对从MPEG2解码器部分输出的数字解码图像进行重新编码。 从重新编码的反编码参数反映从控制部分提供的编码信息。 MPEG2标准和DV标准之间的转码也可以通过布置与DV标准相对应的解码器或编码器代替MPEG2解码器部分或MPEG2编码器部分来执行。