公开(公告)号：US20080133887A1

公开(公告)日：2008-06-05

申请号：US11987704

申请日：2007-12-04

申请人： Toyohiko Yoshida ,  Akira Yamada ,  Hisakazu Sato

发明人： Toyohiko Yoshida ,  Akira Yamada ,  Hisakazu Sato

IPC分类号： G06F9/38

CPC分类号： G06F9/3814 ,  G06F7/5443 ,  G06F9/3802 ,  G06F9/381 ,  G06F9/3822 ,  G06F9/3875

摘要： When fetching an instruction from a plurality of memory banks, a first pipeline cycle corresponding to selection of a memory bank and a second pipeline cycle corresponding to instruction readout are generated to carry out a pipeline process. Only the selected memory bank can be precharged to allow reduction of power consumption. Since the first and second pipeline cycles are effected in parallel, the throughput of the instruction memory can be improved.

公开(公告)号：US07694109B2

公开(公告)日：2010-04-06

申请号：US11987704

申请日：2007-12-04

申请人： Toyohiko Yoshida ,  Akira Yamada ,  Hisakazu Sato

发明人： Toyohiko Yoshida ,  Akira Yamada ,  Hisakazu Sato

IPC分类号： G06F12/06

CPC分类号： G06F9/3814 ,  G06F7/5443 ,  G06F9/3802 ,  G06F9/381 ,  G06F9/3822 ,  G06F9/3875

摘要： When fetching an instruction from a plurality of memory banks, a first pipeline cycle corresponding to selection of a memory bank and a second pipeline cycle corresponding to instruction readout are generated to carry out a pipeline process. Only the selected memory bank can be precharged to allow reduction of power consumption. Since the first and second pipeline cycles are effected in parallel, the throughput of the instruction memory can be improved.

摘要翻译： 当从多个存储体获取指令时，生成对应于存储器组的选择的第一流水线循环和对应于指令读出的第二流水线循环，以执行流水线处理。 只有选定的存储体可以被预先充电，以减少功耗。 由于第一和第二流水线周期是并行实现的，因此可以提高指令存储器的吞吐量。

公开(公告)号：US07346760B2

公开(公告)日：2008-03-18

申请号：US09855594

申请日：2001-05-16

申请人： Toyohiko Yoshida ,  Akira Yamada ,  Hisakazu Sato

发明人： Toyohiko Yoshida ,  Akira Yamada ,  Hisakazu Sato

IPC分类号： G06F9/30 ,  G06F9/38

CPC分类号： G06F9/3814 ,  G06F7/5443 ,  G06F9/3802 ,  G06F9/381 ,  G06F9/3822 ,  G06F9/3875

摘要： When fetching an instruction from a plurality of memory banks, a first pipeline cycle corresponding to selection of a memory bank and a second pipeline cycle corresponding to instruction readout are generated to carry out a pipeline process. Only the selected memory bank can be precharged to allow reduction of power consumption. Since the first and second pipeline cycles are effected in parallel, the throughput of the instruction memory can be improved.

摘要翻译： 当从多个存储体获取指令时，生成对应于存储器组的选择的第一流水线循环和对应于指令读出的第二流水线循环，以执行流水线处理。 只有选定的存储体可以被预先充电，以减少功耗。 由于第一和第二流水线周期是并行实现的，因此可以提高指令存储器的吞吐量。

公开(公告)号：US06779098B2

公开(公告)日：2004-08-17

申请号：US09995835

申请日：2001-11-29

申请人： Hisakazu Sato ,  Isao Minematsu

发明人： Hisakazu Sato ,  Isao Minematsu

IPC分类号： G06F1200

CPC分类号： G06F9/3552 ,  G06F9/345

摘要： A data processing device includes a memory system capable of a plurality of simultaneous accesses, a plurality of address generators each generating an address for accessing the memory system, an addressing register having a plurality of address registers, a data processing unit providing an operation process to the data read from the memory system, and a control unit controlling operations of the plurality of address generators and the data processing unit. The plurality of address generators can generate addresses from a common value in one address register to simultaneously read data designated by the generated addresses from the memory system.

摘要翻译： 数据处理装置包括能够进行多次同时访问的存储器系统，多个地址生成器，每个产生用于访问存储器系统的地址;寻址寄存器，具有多个地址寄存器;数据处理单元，提供操作处理 从存储器系统读取的数据，以及控制多个地址生成器和数据处理单元的操作的控制单元。 多个地址生成器可以从一个地址寄存器中的公共值生成地址，以同时从存储器系统读取由生成的地址指定的数据。

公开(公告)号：US07581054B2

公开(公告)日：2009-08-25

申请号：US11779189

申请日：2007-07-17

申请人： Kesami Hagiwara ,  Takeshi Kataoka ,  Hisakazu Sato ,  Shunichi Iwata ,  Yoshikazu Kiyoshige ,  Akihiko Tomita

发明人： Kesami Hagiwara ,  Takeshi Kataoka ,  Hisakazu Sato ,  Shunichi Iwata ,  Yoshikazu Kiyoshige ,  Akihiko Tomita

IPC分类号： G06F13/14 ,  G06F15/167

CPC分类号： G06F13/364

摘要： In a multiprocessor, one of two local memories can be accessed at a high speed by one of the two processors and also accessed by the other processor. In a multiprocessor, first and second local memories are coupled to first and second processors via first and second local buses. First and second bus bridges are coupled to a system bus and the first and second local buses. First and second bus interface units are coupled to the system bus and the first and second local memories. A high-speed access is made from the first processor to the first local memory via the first local bus. The first local memory is also accessed from the first processor via the first local bus, the first bus bridge, the system bus, and the first and third ports of the second bus interface unit and from the second processor via the second local bus, the second bus bridge, the system bus, and the second and third ports of the first bus interface unit. A high-speed access is made from the second processor to the second local memory via the second local bus. The second local memory is also accessed from the second processor via the second local bus, the second bus bridge, the system bus, and the second and third ports of the first bus interface unit and from the first processor via the first local bus, the first bus bridge, the system bus, and the first and third ports of the second bus interface unit.

摘要翻译： 在多处理器中，两个本地存储器之一可以通过两个处理器之一高速访问，并且还可以由另一个处理器访问。 在多处理器中，第一和第二本地存储器经由第一和第二本地总线耦合到第一和第二处理器。 第一和第二总线桥耦合到系统总线和第一和第二本地总线。 第一和第二总线接口单元耦合到系统总线和第一和第二本地存储器。 通过第一本地总线从第一处理器到第一本地存储器进行高速访问。 第一本地存储器还通过第一局部总线，第一总线桥，系统总线以及第二总线接口单元的第一和第三端口以及经由第二本地总线从第二处理器访问第一本地存储器， 第二总线桥，系统总线，以及第一总线接口单元的第二和第三端口。 通过第二本地总线从第二处理器到第二本地存储器进行高速访问。 第二本地存储器还通过第二本地总线，第二总线桥，系统总线以及第一总线接口单元的第二和第三端口以及经由第一本地总线从第一处理器访问第二本地存储器， 第一总线桥，系统总线，以及第二总线接口单元的第一和第三端口。

公开(公告)号：US07162585B2

公开(公告)日：2007-01-09

申请号：US10686724

申请日：2003-10-17

申请人： Isao Minematsu ,  Hisakazu Sato

发明人： Isao Minematsu ,  Hisakazu Sato

IPC分类号： G06F9/00

CPC分类号： G06F9/3802 ,  G06F9/3814

摘要： An address range of consecutive instructions stored in an instruction buffer is set in an address table. A determination unit determines whether an instruction address outputted from a CPU core falls within the address range set in the address table. A selector selectively outputs an instruction code stored in the instruction buffer and an instruction code stored in an instruction cache in accordance with a determination result of the determination unit. Therefore, in the case where the CPU core fetches an instruction stored in the instruction buffer, an access cycle is guaranteed and an operation of the instruction cache is stopped, thereby making it possible to improve power efficiency.

摘要翻译： 存储在指令缓冲器中的连续指令的地址范围被设置在地址表中。 确定单元确定从CPU核心输出的指令地址是否落在地址表中设置的地址范围内。 选择器根据确定单元的确定结果选择性地输出存储在指令缓冲器中的指令代码和存储在指令高速缓存中的指令代码。 因此，在CPU内核获取存储在指令缓冲器中的指令的情况下，保证访问周期并且停止指令高速缓存的操作，从而可以提高功率效率。

公开(公告)号：US06389524B1

公开(公告)日：2002-05-14

申请号：US09621531

申请日：2000-07-21

申请人： Hisakazu Sato

发明人： Hisakazu Sato

IPC分类号： G06F1204

CPC分类号： G11C15/00 ,  G06F12/04 ,  G11C15/04

摘要： A tag array retains a plurality of tag data, and performs matching of the tag data with a retrieval keyword. The tag array includes matching circuits provided corresponding to the tag data. Each of the matching circuits has CM and CC cells provided corresponding to a plurality of bits of the corresponding tag data. Each CM cell retains a corresponding bit of the tag data, and performs matching of the retaining bit with a corresponding bit of the retrieval keyword. Each CC cell, not only functions as the CM cell, but also retains a comparison condition signal input in advance, and invalidates, according to the comparison condition signal, the mismatch detected between corresponding bits of the tag data and the retrieval keyword. As a result, it becomes possible to variably set the number of bits, of an input retrieval keyword, being matched with the tag data.

摘要翻译： 标签阵列保留多个标签数据，并且执行标签数据与检索关键字的匹配。 标签阵列包括对应于标签数据提供的匹配电路。 每个匹配电路具有相应于相应标签数据的多个位的CM和CC单元。 每个CM单元保留标签数据的相应位，并且执行保留位与检索关键字的对应位的匹配。 每个CC单元不仅用作CM单元，而且还保留预先输入的比较条件信号，并根据比较条件信号使在标签数据的相应位和检索关键字之间检测到的失配无效。 结果，可以可变地设置与标签数据匹配的输入检索关键字的位数。

公开(公告)号：US5280597A

公开(公告)日：1994-01-18

申请号：US676668

申请日：1991-03-28

申请人： Hidehiro Takata ,  Yoshihiro Seguchi ,  Hisakazu Sato ,  Shinji Komori

发明人： Hidehiro Takata ,  Yoshihiro Seguchi ,  Hisakazu Sato ,  Shinji Komori

IPC分类号： G06F9/38 ,  G06F13/42 ,  G06F15/78 ,  G06F13/00 ,  G11C19/00

CPC分类号： G06F15/8061 ,  G06F13/4239 ,  G06F9/3834 ,  G06F9/3867 ,  G06F9/3869

摘要： An improved self-timed pipeline processor is provided with self-timed data transfer, thereby making it possible to control exclusively the memory reading and memory writing accesses of individual pipeline stages. The self-timed pipeline processor prohibits memory reading during memory writing and vice versa. In addition, the pipeline processor temporarily prevents the transfer of data to a next-accessing pipeline stage when the memory address presently being accessed is the same as the address to be accessed next, thereby preventing malfunction of the processor.

摘要翻译： 改进的自定时流水线处理器具有自定时数据传输，从而使得可以专门地控制各个流水线级的存储器读取和存储器写入访问。 自定时流水线处理器在存储器写入期间禁止存储器读取，反之亦然。 此外，当当前存取的存储器地址与接下来访问的地址相同时，流水线处理器暂时阻止数据传送到下一个访问流水线级，从而防止处理器的故障。

公开(公告)号：US06560697B2

公开(公告)日：2003-05-06

申请号：US10028697

申请日：2001-12-28

申请人： Hisakazu Sato

发明人： Hisakazu Sato

IPC分类号： G06F940

CPC分类号： G06F9/3822 ,  G06F9/30065 ,  G06F9/325

摘要： A data processor configured to repeatedly perform sequential execution of a plurality of instructions in a program in response to a repeat instruction in the program. The data processor includes a counting circuit configured to count every time one instruction of the plurality of instructions is executed; a judgment circuit configured to judge whether the counting circuit counts a predetermined number of times; and an instruction execution control portion configured to control an execution sequence to return to a head instruction of said plurality of instructions following a last instruction in the plurality of instructions in response to a first result output from the judgment circuit indicating that the counting circuit does not count the predetermined number of times.

摘要翻译： 一种数据处理器，被配置为响应于程序中的重复指令，重复执行程序中的多个指令的顺序执行。 数据处理器包括计数电路，配置为每当执行多个指令的一个指令时进行计数; 判断电路，被配置为判断所述计数电路是否计数预定次数; 以及指令执行控制部，其被配置为响应于来自所述判断电路的指示所述计数电路不是的所述第一结果输出，控制执行序列返回到所述多个指令中的最后指令之后的所述多个指令的头指令 计数预定次数。

公开(公告)号：US06345357B1

公开(公告)日：2002-02-05

申请号：US09347004

申请日：1999-07-02

申请人： Hisakazu Sato

发明人： Hisakazu Sato

IPC分类号： G06F940

CPC分类号： G06F9/3822 ,  G06F9/30065 ,  G06F9/325

摘要： An execution control signal generation unit (910) sequentially generates an execution control signal on the basis of an instruction code (907) given through a group (908) of data latches to execute an instruction designated by the instruction code (907) when a repeat end flag (903) is not asserted (instructions have not been yet executed an execution instruction number of times) and negates all the execution control signals, regardless of the indication of the instruction code (907), when the repeat end flag (903) is asserted (instructions have been executed the execution instruction number of times). All the instructions executed while the repeat end flag (903) is asserted are negated. With this configuration, a data processor capable of executing instructions accurately a designated number of times while the instructions included in a predetermined instruction stream are repeatedly executed.

摘要翻译： 执行控制信号生成单元（910）基于通过数据锁存器的组（908）给出的指令代码（907）顺序地生成执行控制信号，以执行由指令代码（907）指定的指令，当重复 结束标志（903）不被断言（指令还没有执行执行指令次数），并且当重复结束标志（903）被忽略时，无论指令代码的指示（907）否定所有执行控制信号） 被断言（指令已执行执行指令次数）。 当重复结束标志（903）被断言时执行的所有指令被否定。 利用这种配置，可以重复执行包括在预定指令流中的指令，从而能够精确地执行指定次数的指令的数据处理器。