公开(公告)号：US06613649B2

公开(公告)日：2003-09-02

申请号：US10002873

申请日：2001-12-05

Applicant: Seng-Keong Victor Lim ,  Feng Chen ,  Alex See ,  Wang Ling Goh

Inventor： Seng-Keong Victor Lim ,  Feng Chen ,  Alex See ,  Wang Ling Goh

IPC: H01L2176

CPC classification number: H01L21/76224

Abstract: A method of manufacturing a shallow trench isolation using a polishing step with reduced dishing. A pad layer, a polish stop layer, a buffer layer and a hard mask layer are formed over a substrate. The hard mask layer has a hard mask opening. We etch a trench opening in the buffer layer, the polish stop layer, the pad layer and form a trench in the substrate using the hard mask layer as an etch mask. We form an oxide trench liner layer along the sidewalls of the trench and an oxide buffer liner layer on the sidewalls of the buffer layer using a thermal oxidation. The hard mask layer prevents the oxidation of the top surface of the buffer layer during the oxidation of the oxide trench liner. This prevents the buffer layer from being consumed by the oxidation and leaves the buffer layer to act in the subsequent chemical-mechanical polish (CMP) step. Next, an insulating layer is formed at least partially filling the trench. The insulating layer is chemical-mechanical polished using the polish stop layer as a stop layer. The buffer layer acts to prevent field oxide dishing during the chemical-mechanical polish.

Abstract translation: 使用具有减少的凹陷的抛光步骤制造浅沟槽隔离的方法。 在衬底上形成焊盘层，抛光停止层，缓冲层和硬掩模层。 硬掩模层具有硬掩模开口。 我们使用硬掩模层作为蚀刻掩模，在缓冲层，抛光停止层，焊盘层中蚀刻沟槽开口，并在衬底中形成沟槽。 我们使用热氧化沿着沟槽的侧壁和缓冲层的侧壁上的氧化物缓冲衬垫层形成氧化物沟槽衬里层。 硬掩模层防止在氧化物沟槽衬垫的氧化期间缓冲层的顶表面的氧化。 这防止缓冲层被氧化消耗，并使缓冲层在随后的化学 - 机械抛光（CMP）步骤中起作用。 接下来，形成至少部分地填充沟槽的绝缘层。 绝缘层使用抛光停止层作为停止层进行化学机械抛光。 缓冲层用于防止化学机械抛光过程中的场氧化物凹陷。

公开(公告)号：US06518133B1

公开(公告)日：2003-02-11

申请号：US10128967

申请日：2002-04-24

Applicant: Alex See ,  Yeow Kheng Lim ,  Cher Liang Randall Cha

Inventor： Alex See ,  Yeow Kheng Lim ,  Cher Liang Randall Cha

IPC: H01L21336

CPC classification number: H01L21/76897 ,  H01L21/28052 ,  H01L21/76877 ,  H01L29/42376 ,  H01L29/6653 ,  H01L29/66553 ,  H01L29/6659 ,  H01L29/7833

Abstract: A method of manufacturing a transistor with a small self aligned gate and self aligned elevated source/drain regions. A first insulating layer is formed over a substrate. A first opening is formed in the first insulating layer to expose the substrate. We form a gate dielectric layer over the substrate in the first opening. Next, first spacers are formed on the sidewalls of the first insulating layer. A gate layer is formed over the first insulating layer, the first spacers, and the gate dielectric layer. We planarize the gate layer to form a gate electrode. The first spacers are removed to form LDD openings. Next, we form lightly doped source/drain regions in the substrate in the LDD openings. Subsequently, second spacers are formed on the sidewalls of the first insulating layer and on the sidewalls of the gate electrode to form S/D openings. Source/drain regions are formed in the substrate in the S/D openings. Next, we form a conductive layer over the substrate at least partially filling the S/D openings. The conductive layer is planarized to form elevated source/drain structures.

Abstract translation: 一种制造具有小的自对准栅极和自对准升高的源极/漏极区域的晶体管的方法。 第一绝缘层形成在衬底上。 在第一绝缘层中形成第一开口以露出衬底。 我们在第一开口中在衬底上形成栅介质层。 接下来，在第一绝缘层的侧壁上形成第一间隔物。 在第一绝缘层，第一间隔物和栅极电介质层上形成栅极层。 我们平面化栅极层以形成栅电极。 去除第一间隔物以形成LDD开口。 接下来，我们在LDD开口中的衬底中形成轻掺杂的源极/漏极区域。 随后，在第一绝缘层的侧壁和栅电极的侧壁上形成第二间隔物以形成S / D开口。 源极/漏极区域形成在S / D开口中的衬底中。 接下来，我们在衬底上形成至少部分填充S / D开口的导电层。 导电层被平坦化以形成升高的源极/漏极结构。

公开(公告)号：US06436833B1

公开(公告)日：2002-08-20

申请号：US09805953

申请日：2001-03-15

Applicant: Chong Hau Pang ,  Chen Feng ,  Alex See ,  Peter Hing

Inventor： Chong Hau Pang ,  Chen Feng ,  Alex See ,  Peter Hing

IPC: H01L2100

CPC classification number: H01L21/76229 ,  H01L21/31053

Abstract: A method of forming shallow trench isolations is described. An etch stop layer is deposited on the surface of a semiconductor substrate. A plurality of isolation trenches are etched through the etch stop layer into the semiconductor substrate to separate active areas. An oxide layer is deposited over the etch stop layer and within the isolation trenches wherein the oxide fills the isolation trenches and overlies the etch stop layer on the active areas. A polysilicon layer is deposited overlying the oxide layer within the isolation trenches and the oxide layer overlying the etch stop layer. The polysilicon layer is polished away until the oxide layer overlying the etch stop layer is exposed and the polysilicon layer remains only overlying the oxide layer in the isolation trenches. The polysilicon layer is oxidized whereby the oxidized polysilicon layer has a height close to the height of the oxide layer overlying the etch stop layer. The oxidized polysilicon layer, the oxide layer overlying the etch stop layer, and the oxide layer in the isolation trenches is polished down until the etch stop layer is reached thereby planarizing the isolation trenches to complete planarized shallow trench isolation regions in the manufacture of an integrated circuit device.

Abstract translation: 描述了形成浅沟槽隔离的方法。 蚀刻停止层沉积在半导体衬底的表面上。 通过蚀刻停止层将多个隔离沟槽蚀刻到半导体衬底中以分离有源区。 氧化物层沉积在蚀刻停止层上方并且在隔离沟槽内，其中氧化物填充隔离沟槽并覆盖有源区上的蚀刻停止层。 沉积在隔离沟槽内的氧化物层和覆盖在蚀刻停止层上的氧化物层的多晶硅层。 将多晶硅层抛光，直到覆盖蚀刻停止层的氧化物层被暴露，并且多晶硅层仅保留在隔离沟槽中的氧化物层上。 多晶硅层被氧化，由此氧化的多晶硅层的高度接近覆盖在蚀刻停止层上的氧化物层的高度。 将氧化的多晶硅层，覆盖蚀刻停止层的氧化物层和隔离沟槽中的氧化物层抛光，直到达到蚀刻停止层，从而平坦化隔离沟槽，从而在制造集成电路的过程中完成平坦化的浅沟槽隔离区域 电路设备。

公开(公告)号：US06391720B1

公开(公告)日：2002-05-21

申请号：US09671509

申请日：2000-09-27

Applicant: Sneedharan Pillai Sneelal ,  Francis Youg Wee Poh ,  James Yong Meng Lee ,  Alex See ,  C. K. Lau ,  Ganesh Shankar Samudra

Inventor： Sneedharan Pillai Sneelal ,  Francis Youg Wee Poh ,  James Yong Meng Lee ,  Alex See ,  C. K. Lau ,  Ganesh Shankar Samudra

IPC: H01L21336

CPC classification number: H01L29/66621 ,  H01L29/66545 ,  H01L29/7834

Abstract: A method for forming a self-aligned, recessed channel, MOSFET device that alleviates the problems due to short channel and hot carrier effects while reducing inter-electrode capacitance is described. A substrate with an active area encompassed by a shallow trench isolation (STI) region is provided. A mask oxide layer is then patterned and etched to expose the substrate and a portion of the STI region. The surface is etched and the mask oxide layer is eroded away while creating a gate recess in the unmasked area. A thin pad oxide layer is then grown overlying the surface followed by a deposition of a thick silicon nitride layer covering the surface and filling the gate recess. The top surface is planarized exposing the pad oxide layer. An additional oxide layer is grown causing the pad oxide layer to thicken. A portion of the silicon nitride layer is etched away and additional oxide layer is again grown causing the pad oxide layer to further thicken. This forms a tapered oxide layer along the sidewalls of the gate recess. The remaining silicon nitride layer is then removed, re-opening the gate recess. A threshold adjust and punch-through implantation is performed into the substrate below the gate recess. The pad oxide layer is then isotropically etched to remove the oxide layer at the bottom of the gate recess and a gate dielectric layer is grown in the bottom of the gate recess. Gate polysilicon is then deposited covering the top surface and filling the gate recess. The top surface is again planarized to expose the substrate. A screen oxide layer is then deposited, followed by light and heavy S/D implantations and annealing. Metalization and passivation complete the fabrication of the MOS transistor device.

公开(公告)号：US06387747B1

公开(公告)日：2002-05-14

申请号：US09867561

申请日：2001-05-31

Applicant: Randall Cha ,  Tae Jong Lee ,  Alex See ,  Lap Chan ,  Chua Chee Tee

Inventor： Randall Cha ,  Tae Jong Lee ,  Alex See ,  Lap Chan ,  Chua Chee Tee

IPC: H01L218244

CPC classification number: H01L28/10 ,  H01L23/5227 ,  H01L27/08 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

Abstract: A method for forming an RF inductor of helical shape having high Q and minimum area. The inductor is fabricated of metal or damascened linear segments formed on three levels of intermetal dielectric layers and interconnected by metal filled vias to form the complete helical shape with electrical continuity.

Abstract translation: 一种形成具有高Q值和最小面积的螺旋形RF电感器的方法。 电感器由形成在三层金属间电介质层上并由金属填充的通孔相互连接形成具有电连续性的完整螺旋形状的金属或镶嵌的线性段制成。

公开(公告)号：US06261935B1

公开(公告)日：2001-07-17

申请号：US09458725

申请日：1999-12-13

Applicant: Alex See ,  Lap Chan ,  Ravi Sundaresan

Inventor： Alex See ,  Lap Chan ,  Ravi Sundaresan

IPC: H01L214763

CPC classification number: H01L29/665 ,  H01L21/28518 ,  H01L21/32053 ,  H01L21/76895 ,  H01L29/66545 ,  H01L29/6656

Abstract: A new method is provided for the creation of contact pads to the poly gate of MOS devices. STI regions are formed, layers of gate oxide, poly and SiN are deposited. The poly gate is patterned and etched leaving a layer of SiN on the surface of the gate. An oxide liner is created, an LDD implant is performed, the gate spacers are created and source/drain region implants are performed. A layer of titanium is deposited and annealed, a salicide etchback is performed to the layer of titanium creating silicided surfaces over the source and drain regions. Inter level dielectric (ILD) is deposited, the layer of ILD is polished down to the SiN layer on the top surface of the gate. The layer of SiN is removed creating a recessed gate structure. A stack of layers of titanium-amorphous silicon-titanium (Ti/Si/Ti) or a layer of WSix is deposited over the layer of ILD filling the recess on top of the gate with Ti/Si/Ti. This Ti/Si/Ti (or WSix) is patterned and etched forming a Ti/Si/Ti stack (or layer of WSix) that partially overlays the layer of ILD while also penetrating the recessed opening of the gate electrode. The layer of Ti/Si/Ti is silicided and forms the contact pad to the gate structure.

Abstract translation: 提供了一种用于向MOS器件的多晶硅栅极创建接触焊盘的新方法。 形成STI区，沉积栅氧化层，聚和SiN层。 多晶硅栅极被图案化和蚀刻，在栅极的表面上留下一层SiN层。 产生氧化物衬垫，执行LDD注入，产生栅极间隔物并执行源极/漏极区域注入。 沉积并退火一层钛，对源层和漏极区产生硅化表面的钛层进行自对准硅蚀刻蚀刻。 层间电介质（ILD）被沉积，ILD层被抛光到栅极顶表面上的SiN层。 去除SiN层，产生凹陷的栅极结构。 在TiD / Si / Ti上在栅极顶部填充凹槽的ILD层上沉积一叠钛 - 非晶硅 - 钛（Ti / Si / Ti）或一层WSix层。 该Ti / Si / Ti（或WSix）被图案化和蚀刻形成Ti / Si / Ti叠层（或WSix层），其部分覆盖ILD层，同时也穿过栅电极的凹入开口。 Ti / Si / Ti层被硅化并形成与栅极结构的接触焊盘。

公开(公告)号：US06204137B1

公开(公告)日：2001-03-20

申请号：US09556386

申请日：2000-04-24

Applicant: Kok Hin Teo ,  Feng Chen ,  Alex See ,  Lap Chan

Inventor： Kok Hin Teo ,  Feng Chen ,  Alex See ,  Lap Chan

IPC: H01L21336

CPC classification number: H01L29/66545 ,  H01L21/76224

Abstract: A new method of forming MOS transistors has been achieved. A pad oxide layer is grown. A silicon nitride layer is deposited. Trenches are etched for planned STI. A trench liner is grown inside of the trenches. A trench oxide layer is deposited filling the trenches. The trench oxide layer is polished down to complete the STI. The same silicon nitride layer is patterned to form dummy gates. A gate liner layer is deposited. Ions are implanted to form lightly doped drain junctions. Sidewall spacers are formed adjacent to the dummy gate electrodes and the shallow trench isolations. Ions are implanted to form the drain and source junctions. An epitaxial silicon layer is grown overlying the source and drain junctions. A metal layer is deposited. The epitaxial silicon layer is converted into sulicide to form silicided source and drain contacts. An interlevel dielectric layer is deposited and polished down to the dummy gates. The dummy gates are etched away to form openings for the planned transistor gates. A gate oxide layer is deposited lining the transistor gate openings. A gate electrode layer is deposited to fill the transistor gate openings. The gate electrode layer is patterned to complete the transistor gates.

Abstract translation: 已经实现了形成MOS晶体管的新方法。 生长衬垫氧化物层。 沉积氮化硅层。 沟槽蚀刻为计划的STI。 在沟槽内生长沟槽衬垫。 沉积填充沟槽的沟槽氧化物层。 将沟槽氧化物层抛光以完成STI。 将相同的氮化硅层图案化以形成伪栅极。 沉积栅极衬垫层。 植入离子以形成轻掺杂的漏极结。 侧壁间隔件形成在与虚拟栅极电极和浅沟槽隔离件相邻处。 植入离子以形成漏极和源极结。 生长在源极和漏极结上方的外延硅层。 沉积金属层。 将外延硅层转化为硅化物以形成硅化源极和漏极触点。 将层间电介质层沉积并抛光到虚拟栅极。 蚀刻掉虚拟栅极以形成预定晶体管栅极的开口。 在晶体管栅极开口上沉积栅极氧化物层。 沉积栅极电极层以填充晶体管栅极开口。 图案化栅极电极层以完成晶体管栅极。

公开(公告)号：US6103594A

公开(公告)日：2000-08-15

申请号：US392393

申请日：1999-09-09

Applicant: Alex See ,  Lap Chan

Inventor： Alex See ,  Lap Chan

IPC: H01L21/762 ,  H01L21/761

CPC classification number: H01L21/76229

Abstract: A method of forming shallow trench isolations is achieved. STI structures so formed do not exhibit isolation oxide thinning due to dishing and erosion problems during the oxide CMP process. A silicon substrate is provided. A first dielectric layer is formed overlying the silicon substrate. A silicon nitride layer is deposited. The silicon nitride layer, the first dielectric layer, and the silicon substrate are etched to form trenches for planned shallow trench isolations. A second dielectric layer is deposited overlying the silicon nitride layer and the trenches. The second dielectric layer is etched to form sidewall spacers inside the trenches. A silicon layer is selectively grown overlying the silicon substrate only where the silicon substrate is exposed in the trenches, and wherein the step of growing is stopped before the silicon layer exceeds the top surface of the silicon nitride layer. A third dielectric layer is deposited overlying the silicon nitride layer, the sidewall spacers, and the silicon layer. The third dielectric layer is polished down to the top surface of the silicon nitride layer to complete the shallow trench isolations where the silicon nitride layer acts as a polishing stop, and the integrated circuit device is completed.

Abstract translation: 实现形成浅沟槽隔离的方法。 如此形成的STI结构在氧化物CMP工艺期间由于凹陷和侵蚀问题而不表现出隔离氧化物变薄。 提供硅衬底。 在硅衬底上形成第一介电层。 沉积氮化硅层。 蚀刻氮化硅层，第一介电层和硅衬底以形成用于规划的浅沟槽隔离的沟槽。 第二介质层沉积在氮化硅层和沟槽之上。 蚀刻第二电介质层以在沟槽内形成侧壁间隔物。 只有在硅衬底暴露在沟槽中的硅衬底上选择性地生长硅层，并且其中在硅层超过氮化硅层的顶表面之前停止生长步骤。 第三电介质层沉积在氮化硅层，侧壁间隔物和硅层上。 第三电介质层被抛光到氮化硅层的顶表面，以完成浅沟槽隔离，其中氮化硅层用作抛光停止，并且集成电路器件完成。

公开(公告)号：US09318378B2

公开(公告)日：2016-04-19

申请号：US10923123

申请日：2004-08-21

Applicant: Yeow Kheng Lim ,  Alex See ,  Tae Jong Lee ,  David Vigar ,  Liang Choo Hsia ,  Kin Leong Pey

Inventor： Yeow Kheng Lim ,  Alex See ,  Tae Jong Lee ,  David Vigar ,  Liang Choo Hsia ,  Kin Leong Pey

IPC: H01L21/76 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L23/528 ,  H01L21/0276 ,  H01L21/288 ,  H01L21/3212 ,  H01L21/76802 ,  H01L21/76808 ,  H01L21/76816 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/7685 ,  H01L21/76879 ,  H01L23/5226 ,  H01L23/53228 ,  H01L23/53295 ,  H01L23/562 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method and structure for slots in wide lines to reduce stress. An example embodiment method and structure for is an interconnect structure comprising: interconnect comprising a wide line. The wide line has a first slot. The first slot is spaced a first distance from a via plug so that the first slot relieves stress on the wide line and the via plug. The via plug can contact the wide line from above or below. Another example embodiment is a dual damascene interconnect structure comprising: an dual damascene shaped interconnect comprising a via plug, a first slot and a wide line. The wide line has the first slot. The first slot is spaced a first distance from the via plug so that the first slot relieves stress on the wide line and the via plug.

公开(公告)号：US08766454B2

公开(公告)日：2014-07-01

申请号：US11466018

申请日：2006-08-21

Applicant: Yeow Kheng Lim ,  Randall Cher Liang Cha ,  Alex See ,  Wang Ling Goh

Inventor： Yeow Kheng Lim ,  Randall Cher Liang Cha ,  Alex See ,  Wang Ling Goh

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L21/76897 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit is provided having a base with a first dielectric layer formed thereon. A second dielectric layer is formed over the first dielectric layer. A third dielectric layer is formed in spaced-apart strips over the second dielectric layer. A first trench opening is formed through the first and second dielectric layers between the spaced-apart strips of the third dielectric layer. A second trench opening is formed contiguously with the first trench opening through the first dielectric layer between the spaced-apart strips of the third dielectric layer. Conductor metals in the trench openings form self-aligned trench interconnects.

Abstract translation: 提供一种集成电路，其具有形成在其上的第一电介质层的基极。 在第一电介质层上形成第二电介质层。 第三电介质层形成在第二电介质层上的间隔开的条带中。 第一沟槽开口通过第三和第二电介质层形成在第三介电层间隔开的条之间。 第二沟槽开口与通过第一介电层的第一沟槽开口连续地形成在第三介电层的间隔开的条之间。 沟槽开口中的导体金属形成自对准沟槽互连。