公开(公告)号：US20050156269A1

公开(公告)日：2005-07-21

申请号：US11081908

申请日：2005-03-15

Applicant: Pooi Lee ,  Kin Pey ,  Alex See ,  Lap Chan

Inventor： Pooi Lee ,  Kin Pey ,  Alex See ,  Lap Chan

IPC: H01L21/265 ,  H01L21/285 ,  H01L21/336 ,  H01L29/49 ,  H01L27/095

CPC classification number: H01L29/665 ,  H01L21/26506 ,  H01L21/28518 ,  H01L29/4933

Abstract: A method and apparatus for performing nickel salicidation is disclosed. The nickel salicide process typically includes: forming a processed substrate including partially fabricated integrated circuit components and a silicon substrate; incorporating nitrogen into the processed substrate; depositing nickel onto the processed substrate; annealing the processed substrate so as to form nickel mono-silicide; removing the unreacted nickel; and performing a series procedures to complete integrated circuit fabrication. This nickel salicide process increases the annealing temperature range for which a continuous, thin nickel mono-silicide layer can be formed on silicon by salicidation. It also delays the onset of agglomeration of nickel mono-silicide thin-films to a higher annealing temperature. Moreover, this nickel salicide process delays the transformation from nickel mono-silicide to higher resistivity nickel di-silicide, to higher annealing temperature. It also reduces nickel enhanced poly-silicon grain growth to prevent layer inversion. Some embodiments of this nickel salicide process may be used in an otherwise standard salicide process, to form integrated circuit devices with low resistivity transistor gate electrodes and source/drain contacts.

公开(公告)号：US06680239B1

公开(公告)日：2004-01-20

申请号：US09624025

申请日：2000-07-24

Applicant: Cher Liang Cha ,  Kok Keng Ong ,  Alex See ,  Lap Chan

Inventor： Cher Liang Cha ,  Kok Keng Ong ,  Alex See ,  Lap Chan

IPC: H01L2176

CPC classification number: H01L21/76237

Abstract: A method for forming shallow trench isolation (STI) with a higher aspect ratio is given. This method allows the formation of narrower and deeper trench isolation regions while avoiding substrate damage due to excessive etching and severe microloading effects. In addition, it yields uniform depth trenches while avoiding problems of etch residue at the bottom of the trench. This method is achieved by using a process where a trench is etched, and an oxide layer grown along the bottom and sidewalls of the trench. Oxygen or field isolation ions are then implanted into the bottom of the trench. A nitride spacer is then formed along the bottom and sidewalls of the trench, followed by an isotropic etch removing the nitride and oxide from the bottom of the trench. An oxide deposition then fills the trench, followed by a planarization step completing the isolation structure.

Abstract translation: 给出了一种形成具有较高纵横比的浅沟槽隔离（STI）的方法。 该方法允许形成更窄和更深的沟槽隔离区域，同时避免由于过度蚀刻和严重的微负载效应引起的基板损伤。 此外，它产生均匀的深度沟槽，同时避免沟槽底部的蚀刻残留问题。 该方法通过使用其中蚀刻沟槽的工艺和沿着沟槽的底部和侧壁生长的氧化物层来实现。 然后将氧或场隔离离子注入到沟槽的底部。 然后沿着沟槽的底部和侧壁形成氮化物间隔物，随后通过各向同性蚀刻从沟槽的底部去除氮化物和氧化物。 氧化物沉积然后填充沟槽，随后是完成隔离结构的平坦化步骤。

公开(公告)号：US06319767B1

公开(公告)日：2001-11-20

申请号：US09798639

申请日：2001-03-05

Applicant: Randall Cher Liang Cha ,  Tae Jong Lee ,  Alex See ,  Lap Chan ,  Yeow Kheng Lim

Inventor： Randall Cher Liang Cha ,  Tae Jong Lee ,  Alex See ,  Lap Chan ,  Yeow Kheng Lim

IPC: H01L218242

CPC classification number: H01L28/60 ,  H01L21/31122 ,  H01L21/31144 ,  H01L21/32136 ,  H01L21/32139

Abstract: A method for fabricating a metal-insulator-metal capacitor wherein top metal corner shaping during patterning is eliminated is described. An insulating layer is provided overlying a semiconductor substrate. A composite metal stack is formed comprising a first metal layer overlying the insulating layer, a capacitor dielectric layer overlying the first metal layer, a second metal layer overlying the capacitor dielectric layer, and a hard mask layer overlying the second metal layer. A first photoresist mask is formed overlying the hard mask layer. The composite metal stack is patterned using the first photoresist mask as an etching mask whereby the patterned first metal layer forms a bottom electrode of the capacitor. A portion of the first photoresist mask is removed by plasma ashing to form a second photoresist mask narrower than the first photoresist mask. The hard mask layer is patterned using the second photoresist mask as an etching mask. The second metal layer is patterned using the hard mask layer as an etching mask whereby the second metal layer forms a top electrode of the capacitor to complete fabrication of a metal-insulator-metal capacitor.

Abstract translation: 描述了一种用于制造金属 - 绝缘体 - 金属电容器的方法，其中消除了图案化期间的顶部金属角成形。 绝缘层设置在半导体衬底上。 形成复合金属堆叠，其包括覆盖绝缘层的第一金属层，覆盖第一金属层的电容器电介质层，覆盖电容器电介质层的第二金属层和覆盖第二金属层的硬掩模层。 第一光致抗蚀剂掩模形成在硬掩模层上。 使用第一光致抗蚀剂掩模将复合金属堆叠图案化为蚀刻掩模，由此图案化的第一金属层形成电容器的底部电极。 通过等离子体灰化除去第一光致抗蚀剂掩模的一部分，以形成比第一光致抗蚀剂掩模窄的第二光刻胶掩模。 使用第二光致抗蚀剂掩模将硬掩模层图案化为蚀刻掩模。 使用硬掩模层作为蚀刻掩模对第二金属层进行构图，由此第二金属层形成电容器的顶部电极，以完成金属 - 绝缘体 - 金属电容器的制造。

公开(公告)号：US07030451B2

公开(公告)日：2006-04-18

申请号：US11081908

申请日：2005-03-15

Applicant: Pooi See Lee ,  Kin Leong Pey ,  Alex See ,  Lap Chan

Inventor： Pooi See Lee ,  Kin Leong Pey ,  Alex See ,  Lap Chan

IPC: H01L29/78

CPC classification number: H01L29/665 ,  H01L21/26506 ,  H01L21/28518 ,  H01L29/4933

Abstract: A method and apparatus for performing nickel salicidation is disclosed. The nickel salicide process typically includes: forming a processed substrate including partially fabricated integrated circuit components and a silicon substrate; incorporating nitrogen into the processed substrate; depositing nickel onto the processed substrate; annealing the processed substrate so as to form nickel mono-silicide; removing the unreacted nickel; and performing a series procedures to complete integrated circuit fabrication. This nickel salicide process increases the annealing temperature range for which a continuous, thin nickel mono-silicide layer can be formed on silicon by salicidation. It also delays the onset of agglomeration of nickel mono-silicide thin-films to a higher annealing temperature. Moreover, this nickel salicide process delays the transformation from nickel mono-silicide to higher resistivity nickel di-silicide, to higher annealing temperature. It also reduces nickel enhanced poly-silicon grain growth to prevent layer inversion. Some embodiments of this nickel salicide process may be used in an otherwise standard salicide process, to form integrated circuit devices with low resistivity transistor gate electrodes and source/drain contacts.

公开(公告)号：US06777329B2

公开(公告)日：2004-08-17

申请号：US09838513

申请日：2001-04-20

Applicant: Shaoyin Chen ,  Ze Xiang Shen ,  Alex See ,  Lap Chan

Inventor： Shaoyin Chen ,  Ze Xiang Shen ,  Alex See ,  Lap Chan

IPC: H01L2144

CPC classification number: H01L21/28518 ,  H01L21/268 ,  H01L21/28052 ,  H01L29/665

Abstract: A novel method for forming a C54 phase titanium disilicide film in the fabrication of an integrated circuit is described. A semiconductor substrate is provided having silicon regions to be silicided. A titanium layer is deposited overlying the silicon regions to be silicided. The substrate is subjected to a first annealing whereby the titanium is transformed to phase C40 titanium disilicide where it overlies the silicon regions and wherein the titanium not overlying the silicon regions is unreacted. The unreacted titanium layer is removed. The substrate is subjected to a second annealing whereby the phase C40 titanium disilicide is transformed to phase C54 titanium disilicide to complete formation of a phase 54 titanium disilicide film in the manufacture of an integrated circuit.

Abstract translation: 描述了在制造集成电路中形成C54相二硅化钛膜的新颖方法。 提供具有要被硅化的硅区域的半导体衬底。 沉积钛层以硅化硅层。 对基板进行第一退火，由此将钛转化为相C40二硅化钛，其中它覆盖在硅区域上，并且其中不覆盖硅区域的钛是未反应的。 去除未反应的钛层。 对基板进行第二次退火，由此在制造集成电路中相C40二硅化钛转变为C54二硅化钛以完成形成54相的二硅化钛膜。

公开(公告)号：US06387747B1

公开(公告)日：2002-05-14

申请号：US09867561

申请日：2001-05-31

Applicant: Randall Cha ,  Tae Jong Lee ,  Alex See ,  Lap Chan ,  Chua Chee Tee

Inventor： Randall Cha ,  Tae Jong Lee ,  Alex See ,  Lap Chan ,  Chua Chee Tee

IPC: H01L218244

CPC classification number: H01L28/10 ,  H01L23/5227 ,  H01L27/08 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

Abstract: A method for forming an RF inductor of helical shape having high Q and minimum area. The inductor is fabricated of metal or damascened linear segments formed on three levels of intermetal dielectric layers and interconnected by metal filled vias to form the complete helical shape with electrical continuity.

Abstract translation: 一种形成具有高Q值和最小面积的螺旋形RF电感器的方法。 电感器由形成在三层金属间电介质层上并由金属填充的通孔相互连接形成具有电连续性的完整螺旋形状的金属或镶嵌的线性段制成。

公开(公告)号：US06261935B1

公开(公告)日：2001-07-17

申请号：US09458725

申请日：1999-12-13

Applicant: Alex See ,  Lap Chan ,  Ravi Sundaresan

Inventor： Alex See ,  Lap Chan ,  Ravi Sundaresan

IPC: H01L214763

CPC classification number: H01L29/665 ,  H01L21/28518 ,  H01L21/32053 ,  H01L21/76895 ,  H01L29/66545 ,  H01L29/6656

Abstract: A new method is provided for the creation of contact pads to the poly gate of MOS devices. STI regions are formed, layers of gate oxide, poly and SiN are deposited. The poly gate is patterned and etched leaving a layer of SiN on the surface of the gate. An oxide liner is created, an LDD implant is performed, the gate spacers are created and source/drain region implants are performed. A layer of titanium is deposited and annealed, a salicide etchback is performed to the layer of titanium creating silicided surfaces over the source and drain regions. Inter level dielectric (ILD) is deposited, the layer of ILD is polished down to the SiN layer on the top surface of the gate. The layer of SiN is removed creating a recessed gate structure. A stack of layers of titanium-amorphous silicon-titanium (Ti/Si/Ti) or a layer of WSix is deposited over the layer of ILD filling the recess on top of the gate with Ti/Si/Ti. This Ti/Si/Ti (or WSix) is patterned and etched forming a Ti/Si/Ti stack (or layer of WSix) that partially overlays the layer of ILD while also penetrating the recessed opening of the gate electrode. The layer of Ti/Si/Ti is silicided and forms the contact pad to the gate structure.

Abstract translation: 提供了一种用于向MOS器件的多晶硅栅极创建接触焊盘的新方法。 形成STI区，沉积栅氧化层，聚和SiN层。 多晶硅栅极被图案化和蚀刻，在栅极的表面上留下一层SiN层。 产生氧化物衬垫，执行LDD注入，产生栅极间隔物并执行源极/漏极区域注入。 沉积并退火一层钛，对源层和漏极区产生硅化表面的钛层进行自对准硅蚀刻蚀刻。 层间电介质（ILD）被沉积，ILD层被抛光到栅极顶表面上的SiN层。 去除SiN层，产生凹陷的栅极结构。 在TiD / Si / Ti上在栅极顶部填充凹槽的ILD层上沉积一叠钛 - 非晶硅 - 钛（Ti / Si / Ti）或一层WSix层。 该Ti / Si / Ti（或WSix）被图案化和蚀刻形成Ti / Si / Ti叠层（或WSix层），其部分覆盖ILD层，同时也穿过栅电极的凹入开口。 Ti / Si / Ti层被硅化并形成与栅极结构的接触焊盘。

公开(公告)号：US06204137B1

公开(公告)日：2001-03-20

申请号：US09556386

申请日：2000-04-24

Applicant: Kok Hin Teo ,  Feng Chen ,  Alex See ,  Lap Chan

Inventor： Kok Hin Teo ,  Feng Chen ,  Alex See ,  Lap Chan

IPC: H01L21336

CPC classification number: H01L29/66545 ,  H01L21/76224

Abstract: A new method of forming MOS transistors has been achieved. A pad oxide layer is grown. A silicon nitride layer is deposited. Trenches are etched for planned STI. A trench liner is grown inside of the trenches. A trench oxide layer is deposited filling the trenches. The trench oxide layer is polished down to complete the STI. The same silicon nitride layer is patterned to form dummy gates. A gate liner layer is deposited. Ions are implanted to form lightly doped drain junctions. Sidewall spacers are formed adjacent to the dummy gate electrodes and the shallow trench isolations. Ions are implanted to form the drain and source junctions. An epitaxial silicon layer is grown overlying the source and drain junctions. A metal layer is deposited. The epitaxial silicon layer is converted into sulicide to form silicided source and drain contacts. An interlevel dielectric layer is deposited and polished down to the dummy gates. The dummy gates are etched away to form openings for the planned transistor gates. A gate oxide layer is deposited lining the transistor gate openings. A gate electrode layer is deposited to fill the transistor gate openings. The gate electrode layer is patterned to complete the transistor gates.

Abstract translation: 已经实现了形成MOS晶体管的新方法。 生长衬垫氧化物层。 沉积氮化硅层。 沟槽蚀刻为计划的STI。 在沟槽内生长沟槽衬垫。 沉积填充沟槽的沟槽氧化物层。 将沟槽氧化物层抛光以完成STI。 将相同的氮化硅层图案化以形成伪栅极。 沉积栅极衬垫层。 植入离子以形成轻掺杂的漏极结。 侧壁间隔件形成在与虚拟栅极电极和浅沟槽隔离件相邻处。 植入离子以形成漏极和源极结。 生长在源极和漏极结上方的外延硅层。 沉积金属层。 将外延硅层转化为硅化物以形成硅化源极和漏极触点。 将层间电介质层沉积并抛光到虚拟栅极。 蚀刻掉虚拟栅极以形成预定晶体管栅极的开口。 在晶体管栅极开口上沉积栅极氧化物层。 沉积栅极电极层以填充晶体管栅极开口。 图案化栅极电极层以完成晶体管栅极。

公开(公告)号：US6103594A

公开(公告)日：2000-08-15

申请号：US392393

申请日：1999-09-09

Applicant: Alex See ,  Lap Chan

Inventor： Alex See ,  Lap Chan

IPC: H01L21/762 ,  H01L21/761

CPC classification number: H01L21/76229

Abstract: A method of forming shallow trench isolations is achieved. STI structures so formed do not exhibit isolation oxide thinning due to dishing and erosion problems during the oxide CMP process. A silicon substrate is provided. A first dielectric layer is formed overlying the silicon substrate. A silicon nitride layer is deposited. The silicon nitride layer, the first dielectric layer, and the silicon substrate are etched to form trenches for planned shallow trench isolations. A second dielectric layer is deposited overlying the silicon nitride layer and the trenches. The second dielectric layer is etched to form sidewall spacers inside the trenches. A silicon layer is selectively grown overlying the silicon substrate only where the silicon substrate is exposed in the trenches, and wherein the step of growing is stopped before the silicon layer exceeds the top surface of the silicon nitride layer. A third dielectric layer is deposited overlying the silicon nitride layer, the sidewall spacers, and the silicon layer. The third dielectric layer is polished down to the top surface of the silicon nitride layer to complete the shallow trench isolations where the silicon nitride layer acts as a polishing stop, and the integrated circuit device is completed.

Abstract translation: 实现形成浅沟槽隔离的方法。 如此形成的STI结构在氧化物CMP工艺期间由于凹陷和侵蚀问题而不表现出隔离氧化物变薄。 提供硅衬底。 在硅衬底上形成第一介电层。 沉积氮化硅层。 蚀刻氮化硅层，第一介电层和硅衬底以形成用于规划的浅沟槽隔离的沟槽。 第二介质层沉积在氮化硅层和沟槽之上。 蚀刻第二电介质层以在沟槽内形成侧壁间隔物。 只有在硅衬底暴露在沟槽中的硅衬底上选择性地生长硅层，并且其中在硅层超过氮化硅层的顶表面之前停止生长步骤。 第三电介质层沉积在氮化硅层，侧壁间隔物和硅层上。 第三电介质层被抛光到氮化硅层的顶表面，以完成浅沟槽隔离，其中氮化硅层用作抛光停止，并且集成电路器件完成。

公开(公告)号：US06355563B1

公开(公告)日：2002-03-12

申请号：US09798652

申请日：2001-03-05

Applicant: Randall Cher Liang Cha ,  Alex See ,  Yeow Kheng Lim ,  Tae Jong Lee ,  Lap Chan

Inventor： Randall Cher Liang Cha ,  Alex See ,  Yeow Kheng Lim ,  Tae Jong Lee ,  Lap Chan

IPC: H01L2144

CPC classification number: H01L21/76802 ,  H01L21/76825 ,  H01L21/76831 ,  H01L21/76832

Abstract: A method to integrate low dielectric constant dielectric materials with copper metallization is described. A metal line is provided overlying a semiconductor substrate and having a nitride capping layer thereover. A polysilicon layer is deposited over the nitride layer and patterned to form dummy vias. A dielectric liner layer is conformally deposited overlying the nitride layer and dummy vias. A dielectric layer having a low dielectric constant is spun-on overlying the liner layer and covering the dummy vias. The dielectric layer is polished down whereby the dummy vias are exposed. Thereafter, the dielectric layer is cured whereby a cross-linked surface layer is formed. The dummy vias are removed thereby exposing a portion of the nitride layer within the via openings. The exposed nitride layer is removed. The via openings are filled with a copper layer which is planarized to complete copper metallization in the fabrication of an integrated circuit device.

Abstract translation: 描述了一种将低介电常数电介质材料与铜金属化相结合的方法。 金属线设置在半导体衬底上并且在其上具有氮化物覆盖层。 多晶硅层沉积在氮化物层上并被图案化以形成虚拟通孔。 电介质衬垫层共形沉积在氮化物层和虚拟通孔之上。 将具有低介电常数的介电层旋涂在衬层上并覆盖虚拟通孔。 抛光电介质层，从而暴露虚拟通孔。 此后，电介质层被固化，由此形成交联表面层。 去除虚设通孔，从而将通孔的一部分氮化物层露出。 去除暴露的氮化物层。 通孔开口填充有铜层，该铜层在集成电路器件的制造中被平坦化以完成铜金属化。