公开(公告)号：US11677006B2

公开(公告)日：2023-06-13

申请号：US17141273

申请日：2021-01-05

申请人： KABUSHIKI KAISHA TOSHIBA ,  OSAKA UNIVERSITY

发明人： Toshiki Hikosaka ,  Shinya Nunoue ,  Tomoyuki Tanikawa ,  Ryuji Katayama ,  Masahiro Uemukai

IPC分类号： H01L29/20 ,  H01L21/02 ,  C23C16/30 ,  G02F1/355 ,  G02F1/37

CPC分类号： H01L29/2003 ,  C23C16/303 ,  G02F1/3551 ,  G02F1/37 ,  H01L21/0254 ,  H01L21/02389 ,  H01L21/02458

摘要： According to one embodiment, a nitride crystal includes first, second, and third nitride crystal regions. The third nitride crystal region includes Al, and is provided between the first and second nitride crystal regions. A third oxygen concentration in the third nitride crystal region is greater than a first oxygen concentration in the first nitride crystal region and greater than a second oxygen concentration in the second nitride crystal region. A third carbon concentration in the third nitride crystal region is greater than a first carbon concentration in the first nitride crystal region and greater than a second carbon concentration in the second nitride crystal region. A direction of the first nitride crystal region is one of a first orientation from the second nitride crystal region toward the first nitride crystal region or a second orientation from the first nitride crystal region toward the second nitride crystal region.

公开(公告)号：US20190237339A1

公开(公告)日：2019-08-01

申请号：US16377338

申请日：2019-04-08

申请人： Tokyo Electron Limited

发明人： Derek Bassett ,  Wallace P. Printz ,  Antonio L. P. Rotondaro ,  Teruomi Minami ,  Takahiro Furukawa

IPC分类号： H01L21/311 ,  H01L21/67 ,  H01L49/02 ,  H01L21/02 ,  H01L21/4757 ,  H01L21/306

CPC分类号： H01L21/31111 ,  H01L21/02052 ,  H01L21/0214 ,  H01L21/02458 ,  H01L21/30608 ,  H01L21/47573 ,  H01L21/6708 ,  H01L21/67253 ,  H01L28/00

摘要： Techniques are provided to remove the growth of colloidal silica deposits on surfaces of high aspect ratio structures during silicon nitride etch steps. A high selectivity overetch step is used to remove the deposited colloidal silica. The disclosed techniques include the use of phosphoric acid to remove silicon nitride from structures having silicon nitride formed in narrow gap or trench structures having high aspect ratios in which formation of colloidal silica deposits on a surface of the narrow gap or trench through a hydrolysis reaction occurs. A second etch step is used in which the hydrolysis reaction which formed the colloidal silica deposits is reversible, and with the now lower concentration of silica in the nearby phosphoric acid due to the depletion of the silicon nitride, the equilibrium drives the reaction in the reverse direction, dissolving the deposited silica back into solution.

公开(公告)号：US20190221712A1

公开(公告)日：2019-07-18

申请号：US16365521

申请日：2019-03-26

申请人： iBeam Materials, Inc.

发明人： Vladimir Matias ,  Christopher Yung

IPC分类号： H01L33/32 ,  H01L33/64 ,  H01L33/18 ,  H01L21/02 ,  H01L31/00 ,  H01L33/00

CPC分类号： H01L33/32 ,  H01L21/02425 ,  H01L21/02458 ,  H01L21/02488 ,  H01L21/02505 ,  H01L21/02516 ,  H01L21/0254 ,  H01L21/0262 ,  H01L31/00 ,  H01L31/036 ,  H01L33/007 ,  H01L33/12 ,  H01L33/18 ,  H01L33/60 ,  H01L33/644

摘要： A multilayer structure including a hexagonal epitaxial layer, such as GaN or other group III-nitride (III-N) semiconductors, a oriented textured layer, and a non-single crystal substrate, and methods for making the same. The textured layer has a crystalline alignment preferably formed by the ion-beam assisted deposition (IBAD) texturing process and can be biaxially aligned. The in-plane crystalline texture of the textured layer is sufficiently low to allow growth of high quality hexagonal material, but can still be significantly greater than the required in-plane crystalline texture of the hexagonal material. The IBAD process enables low-cost, large-area, flexible metal foil substrates to be used as potential alternatives to single-crystal sapphire and silicon for manufacture of electronic devices, enabling scaled-up roll-to-roll, sheet-to-sheet, or similar fabrication processes to be used. The user is able to choose a substrate for its mechanical and thermal properties, such as how well its coefficient of thermal expansion matches that of the hexagonal epitaxial layer, while choosing a textured layer that more closely lattice matches that layer. Electronic devices such as LEDs can be manufactured from such structures. Because the substrate can act as both a reflector and a heat sink, transfer to other substrates, and use of external reflectors and heat sinks, is not required, greatly reducing costs. Large area devices such as light emitting strips or sheets may be fabricated using this technology.

公开(公告)号：US20190140134A1

公开(公告)日：2019-05-09

申请号：US16182393

申请日：2018-11-06

申请人： Gallium Enterprises Pty Ltd

发明人： Ian MANN ,  Satyanarayan BARIK ,  Joshua David BROWN ,  Danyu LIU

IPC分类号： H01L33/00 ,  H01L33/02 ,  H01L33/06 ,  H01L33/32

CPC分类号： H01L33/007 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/02658 ,  H01L33/025 ,  H01L33/06 ,  H01L33/325

摘要： Methods for fabricating semiconductor devices incorporating an activated p-(Al,In)GaN layer include exposing a p-(Al,In)GaN layer to a gaseous composition of H2 and/or NH3 under conditions that would otherwise passivate the p-(Al,In)GaN layer. The methods do not include subjecting the p-(Al,In)GaN layer to a separate activation step in a low hydrogen or hydrogen-free environment. The methods can be used to fabricate buried activated n/p-(Al,In)GaN tunnel junctions, which can be incorporated into electronic devices.

公开(公告)号：US20190088495A1

公开(公告)日：2019-03-21

申请号：US16044479

申请日：2018-07-24

申请人： MICROLINK DEVICES, INC.

发明人： Christopher Youtsey ,  Robert McCarthy ,  Rekha Reddy

IPC分类号： H01L21/306 ,  H01L21/67 ,  H01L29/20 ,  H01L21/02

CPC分类号： H01L21/30612 ,  H01L21/02389 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/02664 ,  H01L21/30635 ,  H01L21/67075 ,  H01L21/67086 ,  H01L21/78 ,  H01L21/7813 ,  H01L29/2003 ,  H01L31/02363 ,  H01L33/0075 ,  H01L33/22

摘要： Methods and systems for forming a device structure free of a substrate are described. Exemplary embodiments include a device structure comprising of device layers, a release layer, an etch stop layer, and a substrate. The device structure is exposed to photoenhanced wet etch environments to vertically and laterally etch the release layer to separate the device layers from the substrate. The device structure can include a contact layer, an etch stop layer, or both in some embodiments.

公开(公告)号：US20190067512A1

公开(公告)日：2019-02-28

申请号：US16058802

申请日：2018-08-08

申请人： TOYODA GOSEI CO., LTD.

发明人： Koji OKUNO

IPC分类号： H01L33/00 ,  H01L33/12 ,  H01L33/22 ,  H01L33/32 ,  H01L33/42 ,  H01L21/02 ,  C30B25/18 ,  C30B29/40

CPC分类号： H01L33/007 ,  C30B25/165 ,  C30B25/183 ,  C30B25/186 ,  C30B29/403 ,  H01L21/0242 ,  H01L21/0243 ,  H01L21/02458 ,  H01L21/02491 ,  H01L21/02502 ,  H01L21/02513 ,  H01L21/0254 ,  H01L21/0262 ,  H01L21/02661 ,  H01L33/12 ,  H01L33/22 ,  H01L33/32 ,  H01L33/42 ,  H01L2933/0016

摘要： To provide a method for producing a Group III nitride semiconductor light-emitting device, which allows the formation of a high-temperature AlN buffer layer on an uneven substrate. This production method comprises forming an Al layer or Al droplets on the uneven shape of the uneven substrate, forming an AlN buffer layer while nitriding the Al layer; and forming a Group III nitride semiconductor layer on the AlN buffer layer. In the forming an Al layer, the internal pressure of a furnace is 1 kPa to 19 kPa, the temperature of the uneven substrate is 900° C. to 1,500° C., and an organic metal gas containing Al is supplied at a flow rate of 1.5×10−4 mol/min or more.

公开(公告)号：US20190051732A1

公开(公告)日：2019-02-14

申请号：US16050776

申请日：2018-07-31

申请人： IMEC VZW

发明人： Steve Stoffels

IPC分类号： H01L29/66 ,  H01L21/02 ,  H01L29/20 ,  H01L29/778 ,  H01L29/47 ,  H01L21/285

CPC分类号： H01L29/66462 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/02579 ,  H01L21/28581 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/47 ,  H01L29/7786

摘要： An enhancement-mode transistor and method for forming a gate of an enhancement-mode transistor are provided. The method includes: (a) providing a p-doped AlxGayInzN gate layer, consisting of a first part and a second part on top of the first part, above a p-doped Alx′Gay′Inz′N channel layer of an enhancement-mode transistor under construction; and (b) providing a metal gate layer on the top surface of the second part, the metal gate layer being formed of a material such as to form a Schottky barrier with the second part, wherein providing the p-doped AlxGayInzN gate layer comprises the steps of: (a1) growing the first part above the p-doped Alx′Gay′Inz′N channel layer of the enhancement-mode transistor under construction, the first part having an average Mg concentration of at most 3×1019 atoms/cm3, and (a2) growing the second part on the first part, the second part having an average Mg concentration higher than 3×1019 atoms/cm3 and having a top surface having a Mg concentration higher than 6×1019 atoms/cm3.

公开(公告)号：US20190051515A1

公开(公告)日：2019-02-14

申请号：US16077263

申请日：2016-02-26

申请人： SANKEN ELECTRIC CO., LTD. ,  SHIN-ETSU HANDOTAI CO., LTD.

发明人： Hiroshi SHIKAUCHI ,  Ken SATO ,  Masaru SHINOMIYA ,  Keitaro TSUCHIYA ,  Kazunori HAGIMOTO

IPC分类号： H01L21/02 ,  H01L29/20 ,  H01L29/205

CPC分类号： H01L21/0251 ,  H01L21/02381 ,  H01L21/02458 ,  H01L21/02507 ,  H01L21/0254 ,  H01L29/1075 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/66462 ,  H01L29/7786 ,  H01L29/7787

摘要： Semiconductor base including: silicon-based substrate; buffer layer including first and second layers alternately on silicon-based substrate, first layer made of nitride-based compound semiconductor containing first material, second layer made of nitride-based compound semiconductor containing second material having larger lattice constant than first material; channel layer on buffer layer and made of nitride-based compound semiconductor containing second material, buffer layer has: first composition graded layer between at least one of first layers and second layer immediately thereabove, made of nitride-based compound semiconductor whose composition ratio of second material is increased gradually upward, whose composition ratio of first material is decreased gradually upward; second composition graded layer between at least one of second layers and first layer immediately thereabove, made of nitride-based compound semiconductor whose first material is increased gradually upward, whose composition ratio of second material is decreased gradually upward, first composition graded layer is thicker than second composition graded layer.

公开(公告)号：US20190027359A9

公开(公告)日：2019-01-24

申请号：US15965014

申请日：2018-04-27

申请人： NGK INSULATORS, LTD.

发明人： Mikiya ICHIMURA ,  Sota MAEHARA ,  Yoshitaka KURAOKA

IPC分类号： H01L21/02 ,  C23C16/34 ,  C30B29/40 ,  C30B19/02 ,  H01L29/20 ,  H01L29/205 ,  H01L29/778 ,  H01L29/66

CPC分类号： H01L21/02389 ,  C23C16/303 ,  C23C16/34 ,  C30B19/02 ,  C30B29/406 ,  H01L21/02458 ,  H01L21/0251 ,  H01L21/0254 ,  H01L21/0262 ,  H01L21/205 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/205 ,  H01L29/207 ,  H01L29/401 ,  H01L29/66007 ,  H01L29/66462 ,  H01L29/778 ,  H01L29/7786 ,  H01L29/7787 ,  H01L29/812

摘要： Provided is an epitaxial substrate for semiconductor elements which suppresses an occurrence of current collapse. The epitaxial substrate for the semiconductor elements includes: a semi-insulating free-standing substrate formed of GaN being doped with Zn; a buffer layer being adjacent to the free-standing substrate; a channel layer being adjacent to the buffer layer; and a barrier layer being provided on an opposite side of the buffer layer with the channel layer therebetween, wherein the buffer layer is a diffusion suppressing layer that suppresses diffusion of Zn from the free-standing substrate into the channel layer.

公开(公告)号：US20180374699A1

公开(公告)日：2018-12-27

申请号：US15773864

申请日：2016-11-01

申请人： The Regents of the University of California

发明人： Benjamin P. Yonkee ,  Erin C. Young ,  John T. Leonard ,  Tal Margalith ,  James S. Speck ,  Steven P. DenBaars ,  Shuji Nakamura

IPC分类号： H01L21/02 ,  H01L29/15 ,  H01L29/20 ,  H01L29/207 ,  H01L29/36 ,  H01L29/885 ,  H01L31/18 ,  H01L31/0352 ,  H01L31/0304 ,  H01L33/00 ,  H01L33/06 ,  H01L33/32

CPC分类号： H01L21/02584 ,  H01L21/02389 ,  H01L21/02458 ,  H01L21/02505 ,  H01L21/0254 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/02581 ,  H01L21/0262 ,  H01L21/02631 ,  H01L29/15 ,  H01L29/2003 ,  H01L29/207 ,  H01L29/365 ,  H01L29/88 ,  H01L29/885 ,  H01L31/03044 ,  H01L31/035236 ,  H01L31/1856 ,  H01L33/0075 ,  H01L33/04 ,  H01L33/06 ,  H01L33/32

摘要： A III-nitride tunnel junction with a modified p-n interface, wherein the modified p-n interface includes a delta-doped layer to reduce tunneling resistance. The delta-doped layer may be doped using donor atoms comprised of Oxygen (O), Germanium (Ge) or Silicon (Si); acceptor atoms comprised of Magnesium (Mg) or Zinc (Zn); or impurities comprised of Iron (Fe) or Carbon (C).