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804 条记录 (耗时 0.041 秒)

    Twin bit non-volatile memory cells with floating gates in substrate trenches
    41.
    发明授权
    Twin bit non-volatile memory cells with floating gates in substrate trenches 有权

    公开(公告)号：US10600794B2

    公开(公告)日：2020-03-24

    申请号：US16160812

    申请日：2018-10-15

    申请人： Silicon Storage Technology, Inc.

    发明人： Chunming Wang ,  Andy Liu ,  Xian Liu ,  Leo Xing ,  Melvin Diao ,  Nhan Do

    IPC分类号： H01L29/66 ,  H01L29/788 ,  H01L29/423 ,  H01L27/11521 ,  H01L27/11524 ,  H01L21/28

    摘要： A twin bit memory cell includes first and second spaced apart floating gates formed in first and second trenches in the upper surface of a semiconductor substrate. An erase gate, or a pair of erase gates, are disposed over and insulated from the floating gates, respectively. A word line gate is disposed over and insulated from a portion of the upper surface that is between the first and second trenches. A first source region is formed in the substrate under the first trench, and a second source region formed in the substrate under the second trench. A continuous channel region of the substrate extends from the first source region, along a side wall of the first trench, along the portion of the upper surface that is between the first and second trenches, along a side wall of the second trench, and to the second source region.

    System and method for implementing inference engine by optimizing programming operation
    42.
    发明授权
    System and method for implementing inference engine by optimizing programming operation 有权

    公开(公告)号：US10586598B2

    公开(公告)日：2020-03-10

    申请号：US16025039

    申请日：2018-07-02

    申请人： Silicon Storage Technology, Inc.

    发明人： Vipin Tiwari ,  Nhan Do

    IPC分类号： G11C16/06 ,  G11C16/10 ,  G11C16/28

    摘要： A memory device that includes a plurality of memory cells arranged in rows and columns, a plurality of bit lines each connected to one of the columns of memory cells, and a plurality of differential sense amplifiers each having first and second inputs and an output. For each of the differential sense amplifiers, the differential sense amplifier is configured to generate an output signal on the output having an amplitude that is based upon a difference in signal amplitudes on the first and second inputs, the first input is connected to one of the bit lines, and the second input is connected to another one of the bit lines. Alternately, one or more sense amplifiers are configured to detect signal amplitudes on the bit lines, and the device includes calculation circuitry configured to produce output signals each based upon a difference in signal amplitudes on two of the bit lines.

    System and method for implementing configurable convoluted neural networks with flash memories
    44.
    发明授权
    System and method for implementing configurable convoluted neural networks with flash memories 有权

    公开(公告)号：US10580492B2

    公开(公告)日：2020-03-03

    申请号：US16107282

    申请日：2018-08-21

    申请人： Silicon Storage Technology, Inc.

    发明人： Vipin Tiwari ,  Nhan Do

    IPC分类号： G11C16/04 ,  H01L27/11521 ,  H01L27/11524 ,  G06N3/06 ,  G06N3/063 ,  G11C16/24

    摘要： A memory array with memory cells arranged in rows and columns. Each memory cell includes source and drain regions with a channel region there between, a floating gate disposed over a first channel region portion, and a second gate disposed over a second channel region portion. A plurality of bit lines each extends along one of the columns and is electrically connected to the drain regions of a first group of one or more of the memory cells in the column and is electrically isolated from the drain regions of a second group of one or more of the memory cells in the column. A plurality of source lines each is electrically connected to the source regions of the memory cells in one of the columns or rows. A plurality of gate lines each is electrically connected to the second gates of memory cells in one of the columns or rows.

    Array of three-gate flash memory cells with individual memory cell read, program and erase
    47.
    发明授权
    Array of three-gate flash memory cells with individual memory cell read, program and erase 有权

    公开(公告)号：US10460811B2

    公开(公告)日：2019-10-29

    申请号：US16387377

    申请日：2019-04-17

    申请人： Silicon Storage Technology, Inc.

    发明人： Hieu Van Tran ,  Vipin Tiwari ,  Nhan Do

    IPC分类号： G11C11/34 ,  G11C16/14 ,  G11C16/10 ,  G11C16/04

    摘要： A memory device and method of erasing same that includes a substrate of semiconductor material and a plurality of memory cells formed on the substrate and arranged in an array of rows and columns. Each of the memory cells includes spaced apart source and drain regions in the substrate, with a channel region in the substrate extending there between, a floating gate disposed over and insulated from a first portion of the channel region which is adjacent the source region, a select gate disposed over and insulated from a second portion of the channel region which is adjacent the drain region, and a program-erase gate disposed over and insulated from the source region. The program-erase gate lines alone or in combination with the select gate lines, or the source lines, are arranged in the column direction so that each memory cell can be individually programmed, read and erased.