公开(公告)号：US12080593B2

公开(公告)日：2024-09-03

申请号：US17859981

申请日：2022-07-07

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Hsin-Ping Chen ,  Ming-Han Lee ,  Shin-Yi Yang ,  Yung-Hsu Wu ,  Chia-Tien Wu ,  Shau-Lin Shue ,  Min Cao

IPC分类号： H01L21/768 ,  H01L21/321 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

CPC分类号： H01L21/76846 ,  H01L21/76802 ,  H01L21/7684 ,  H01L21/76844 ,  H01L21/76877 ,  H01L21/76879 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53209 ,  H01L23/53252 ,  H01L23/53266 ,  H01L21/3212

摘要： Interconnect structures and method of forming the same are disclosed herein. An exemplary interconnect structure includes a first contact feature in a first dielectric layer, a second dielectric layer over the first dielectric layer, a second contact feature over the first contact feature, a barrier layer between the second dielectric layer and the second contact feature, and a liner between the barrier layer and the second contact feature. An interface between the first contact feature and the second contact feature includes the liner but is free of the barrier layer.

公开(公告)号：US11935783B2

公开(公告)日：2024-03-19

申请号：US17745614

申请日：2022-05-16

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Hsin-Yen Huang ,  Shao-Kuan Lee ,  Cheng-Chin Lee ,  Hai-Ching Chen ,  Shau-Lin Shue

IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC分类号： H01L21/76879 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76807 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76856 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/53295

摘要： Examples of an integrated circuit with an interconnect structure and a method for forming the integrated circuit are provided herein. In some examples, the method includes receiving a workpiece that includes a substrate and an interconnect structure. The interconnect structure includes a first conductive feature disposed within a first inter-level dielectric layer. A blocking layer is selectively formed on the first conductive feature without forming the blocking layer on the first inter-level dielectric layer. An alignment feature is selectively formed on the first inter-level dielectric layer without forming the alignment feature on the blocking layer. The blocking layer is removed from the first conductive feature, and a second inter-level dielectric layer is formed on the alignment feature and on the first conductive feature. The second inter-level dielectric layer is patterned to define a recess for a second conductive feature, and the second conductive feature is formed within the recess.

公开(公告)号：US11929326B2

公开(公告)日：2024-03-12

申请号：US17556134

申请日：2021-12-20

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Shin-Yi Yang ,  Ming-Han Lee ,  Shau-Lin Shue

IPC分类号： H01L23/532 ,  H01L21/324 ,  H01L21/768 ,  H01L23/522

CPC分类号： H01L23/53238 ,  H01L21/324 ,  H01L21/76876 ,  H01L23/5226

摘要： Interconnect structures and method of forming the same are disclosed herein. An exemplary interconnect structure includes a first contact feature in a first dielectric layer, a second dielectric layer over the first dielectric layer, a third dielectric layer over the second dielectric layer, a second contact feature extending through the second dielectric layer and the third dielectric layer, and a graphene layer between the second contact feature and the third dielectric layer.

公开(公告)号：US11860550B2

公开(公告)日：2024-01-02

申请号：US17868398

申请日：2022-07-19

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Tai-I Yang ,  Wei-Chen Chu ,  Hsiang-Wei Liu ,  Shau-Lin Shue ,  Li-Lin Su ,  Yung-Hsu Wu

IPC分类号： G03F7/00 ,  H01L21/768 ,  G03F7/004 ,  G03F7/09

CPC分类号： G03F7/70633 ,  G03F7/0035 ,  G03F7/0043 ,  G03F7/0047 ,  G03F7/094 ,  G03F7/70625 ,  H01L21/7682 ,  H01L21/76807 ,  H01L21/76837 ,  H01L21/76885 ,  H01L21/76897 ,  H01L21/76849

摘要： Photolithography overlay errors are a source of patterning defects, which contribute to low wafer yield. An interconnect formation process that employs a patterning photolithography/etch process with self-aligned interconnects is disclosed herein. The interconnection formation process, among other things, improves a photolithography overlay (OVL) margin since alignment is accomplished on a wider pattern. In addition, the patterning photolithography/etch process supports multi-metal gap fill and low-k dielectric formation with voids.

公开(公告)号：US11742239B2

公开(公告)日：2023-08-29

申请号：US17501523

申请日：2021-10-14

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Shih-Kang Fu ,  Ming-Han Lee ,  Shau-Lin Shue

IPC分类号： H01L21/768 ,  H01L21/321 ,  H01L23/535 ,  H01L23/532

CPC分类号： H01L21/7684 ,  H01L21/3212 ,  H01L21/76805 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76841 ,  H01L21/76843 ,  H01L21/76895 ,  H01L23/535 ,  H01L23/53209 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252

摘要： A method of forming a semiconductor structure includes removing a top portion of a conductive feature disposed in a first dielectric layer and over a semiconductor substrate to form a first recess, depositing a second dielectric layer over the first dielectric layer, where the second dielectric layer includes a first region disposed vertically above the first recess and a second region disposed adjacent the first region, and forming a third dielectric layer over the second dielectric layer. The method further includes subsequently forming openings in the third dielectric layer that extend to expose the second dielectric layer, depositing a conductive material in the openings, and planarizing the conductive material to form conductive features in the first and the second regions, where the planarizing completely removes portions of the third dielectric layer disposed in the second region.

公开(公告)号：US20230073811A1

公开(公告)日：2023-03-09

申请号：US17984443

申请日：2022-11-10

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Hsin-Ping Chen ,  Yung-Hsu Wu ,  Chia-Tien Wu ,  Min Cao ,  Ming-Han Lee ,  Shau-Lin Shue ,  Shin-Yi Yang

IPC分类号： H01L21/768 ,  H01L23/532 ,  H01L23/528 ,  H01L23/522

摘要： Interconnect structures and method of forming the same are disclosed herein. An exemplary interconnect structure includes a first contact feature in a first dielectric layer, a second dielectric layer over the first dielectric layer, a second contact feature over the first contact feature, a barrier layer between the second dielectric layer and the second contact feature, and a liner between the barrier layer and the second contact feature. An interface between the first contact feature and the second contact feature includes the liner but is free of the barrier layer.

公开(公告)号：US11545389B2

公开(公告)日：2023-01-03

申请号：US17083230

申请日：2020-10-28

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Shih-Kang Fu ,  Ming-Han Lee ,  Shau-Lin Shue

IPC分类号： H01L21/768 ,  H01L23/532 ,  H01L23/528

摘要： A semiconductor device is provided. The semiconductor device includes a dielectric layer over a substrate and a contact structure embedded in the dielectric layer. The contact structure includes a diffusion barrier contacting the dielectric layer, the diffusion barrier including a titanium (Ti)-containing alloy. The contact structure further includes a liner on the diffusion barrier, the liner including a noble metal. The contact structure further includes a conductive plug on the liner.

公开(公告)号：US11462470B2

公开(公告)日：2022-10-04

申请号：US16714431

申请日：2019-12-13

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Shin-Yi Yang ,  Ming-Han Lee ,  Shau-Lin Shue

IPC分类号： H01L23/522 ,  H01L23/532 ,  H01L23/528 ,  H01L21/768

摘要： A method for manufacturing a semiconductor structure includes: forming a dielectric layer over a conductive layer on a semiconductor substrate; etching the dielectric layer to form a via hole that exposes the conductive layer; depositing a barrier layer to line the via hole; after depositing the barrier layer, depositing a first metal layer to fill a remainder of the via hole; performing a chemical mechanical polishing (CMP) process on the first metal layer until the barrier layer is exposed; after performing the CMP process, depositing a second metal layer over the barrier layer and the first metal layer; and etching the second metal layer to form a metal line.

公开(公告)号：US20220277996A1

公开(公告)日：2022-09-01

申请号：US17745614

申请日：2022-05-16

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Hsin-Yen Huang ,  Shao-Kuan Lee ,  Cheng-Chin Lee ,  Hai-Ching Chen ,  Shau-Lin Shue

IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L23/532

摘要： Examples of an integrated circuit with an interconnect structure and a method for forming the integrated circuit are provided herein. In some examples, the method includes receiving a workpiece that includes a substrate and an interconnect structure. The interconnect structure includes a first conductive feature disposed within a first inter-level dielectric layer. A blocking layer is selectively formed on the first conductive feature without forming the blocking layer on the first inter-level dielectric layer. An alignment feature is selectively formed on the first inter-level dielectric layer without forming the alignment feature on the blocking layer. The blocking layer is removed from the first conductive feature, and a second inter-level dielectric layer is formed on the alignment feature and on the first conductive feature. The second inter-level dielectric layer is patterned to define a recess for a second conductive feature, and the second conductive feature is formed within the recess.

公开(公告)号：US11355430B2

公开(公告)日：2022-06-07

申请号：US16885378

申请日：2020-05-28

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Ting-Ya Lo ,  Chi-Lin Teng ,  Hai-Ching Chen ,  Hsin-Yen Huang ,  Shau-Lin Shue ,  Shao-Kuan Lee ,  Cheng-Chin Lee

IPC分类号： H01L23/522 ,  H01L23/538 ,  H01L21/768

摘要： Some embodiments relate to a semiconductor structure including an inter-level dielectric (ILD) layer overlying a substrate. A conductive via is disposed within the ILD layer. A plurality of conductive wires overlie the ILD layer. The plurality of conductive wires includes a first conductive wire laterally offset a second conductive wire. A dielectric structure is disposed laterally between the first and second conductive wires. The dielectric structure includes a first dielectric liner, a dielectric layer, and an air-gap. The air-gap is disposed between an upper surface of the first dielectric liner and a lower surface of the dielectric layer. A dielectric capping layer is disposed along an upper surface of the dielectric structure. The dielectric capping layer continuously extends between opposing sidewalls of the dielectric structure and is laterally offset from the plurality of conductive wires.