公开(公告)号：US09799558B2

公开(公告)日：2017-10-24

申请号：US14942386

申请日：2015-11-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsi-Wen Tien ,  Carlos H. Diaz ,  Chung-Ju Lee ,  Shau-Lin Shue ,  Tien-I Bao

IPC: H01L21/768 ,  H01L21/311 ,  H01L21/288 ,  H01L21/3105 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/7688 ,  H01L21/288 ,  H01L21/31051 ,  H01L21/31111 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/76808 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76877 ,  H01L21/76885 ,  H01L23/5226 ,  H01L23/53228 ,  H01L2221/1063

Abstract: A method for manufacturing a semiconductor structure is provided. The method includes forming a first dielectric layer over a substrate and forming a sacrificial layer over the first dielectric layer. The method further includes forming an opening in the sacrificial layer and etching the first dielectric layer to form a via hole through the opening. The method further includes forming a conductive structure in the via hole and the opening and removing the sacrificial layer to expose an upper portion of the conductive structure. The method further includes forming a second dielectric layer around the upper portion of the conductive material.

公开(公告)号：US09728503B2

公开(公告)日：2017-08-08

申请号：US14926469

申请日：2015-10-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chao-Hsien Peng ,  Chi-Liang Kuo ,  Ming-Han Lee ,  Hsiang-Huan Lee ,  Shau-Lin Shue

IPC: H01L21/00 ,  H01L23/00 ,  H01L23/532 ,  H01L23/522 ,  H01L21/768 ,  H01L23/528

CPC classification number: H01L23/53238 ,  H01L21/76805 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76844 ,  H01L21/76847 ,  H01L21/76855 ,  H01L21/76877 ,  H01L21/76879 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53209 ,  H01L23/53223 ,  H01L23/53252 ,  H01L23/53261 ,  H01L23/53266 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In some embodiments, the present disclosure relates to a conductive interconnect layer. The conductive interconnect layer has a dielectric layer disposed over a substrate. An opening with an upper portion above a horizontal plane and a lower portion below the horizontal plane extends downwardly through the dielectric layer. A first conductive layer fills the lower portion of the opening. An upper barrier layer is disposed over the first conductive layer covering bottom and sidewall surfaces of the upper portion of the opening. A second conductive layer is disposed over the upper barrier layer filling the upper portion of the opening.

公开(公告)号：US20160049373A1

公开(公告)日：2016-02-18

申请号：US14926469

申请日：2015-10-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chao-Hsien Peng ,  Chi-Liang Kuo ,  Ming-Han Lee ,  Hsiang-Huan Lee ,  Shau-Lin Shue

IPC: H01L23/532 ,  H01L23/522 ,  H01L23/528 ,  H01L21/768

CPC classification number: H01L23/53238 ,  H01L21/76805 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76844 ,  H01L21/76847 ,  H01L21/76855 ,  H01L21/76877 ,  H01L21/76879 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53209 ,  H01L23/53223 ,  H01L23/53252 ,  H01L23/53261 ,  H01L23/53266 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In some embodiments, the present disclosure relates to a conductive interconnect layer. The conductive interconnect layer has a dielectric layer disposed over a substrate. An opening with an upper portion above a horizontal plane and a lower portion below the horizontal plane extends downwardly through the dielectric layer. A first conductive layer fills the lower portion of the opening. An upper barrier layer is disposed over the first conductive layer covering bottom and sidewall surfaces of the upper portion of the opening. A second conductive layer is disposed over the upper barrier layer filling the upper portion of the opening.

Abstract translation: 在一些实施例中，本公开涉及导电互连层。 导电互连层具有设置在基板上的电介质层。 具有在水平面上方的上部和水平面下方的下部的开口向下延伸穿过介电层。 第一导电层填充开口的下部。 上阻挡层设置在覆盖开口上部的底部和侧壁表面的第一导电层上。 第二导电层设置在填充开口的上部的上阻挡层上。

公开(公告)号：US20240379559A1

公开(公告)日：2024-11-14

申请号：US18780834

申请日：2024-07-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shin-Yi Yang ,  Yu-Chen Chan ,  Ming-Han Lee ,  Hai-Ching Chen ,  Shau-Lin Shue

IPC: H01L23/532 ,  H01L21/768 ,  H01L23/522

Abstract: A semiconductor structure is provided. The semiconductor structure includes a first conductive feature and a second conductive feature disposed in an interlayer dielectric (ILD) layer. The semiconductor structure includes a first graphene layer disposed over the first conductive feature and a second graphene layer disposed over a portion of the second conductive feature. An etch-stop layer (ESL) is horizontally interposed between the first graphene layer and the second graphene layer. A side surface of the first or the second graphene layer directly contacts a side surface of the ESL. A third conductive feature is electrically coupled to the second conductive feature. The third conductive feature is separated from the first graphene layer by a portion of the ESL, and the third conductive feature also directly contacts a top surface of the ESL.

公开(公告)号：US12080593B2

公开(公告)日：2024-09-03

申请号：US17859981

申请日：2022-07-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Ping Chen ,  Ming-Han Lee ,  Shin-Yi Yang ,  Yung-Hsu Wu ,  Chia-Tien Wu ,  Shau-Lin Shue ,  Min Cao

IPC: H01L21/768 ,  H01L21/321 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L21/76846 ,  H01L21/76802 ,  H01L21/7684 ,  H01L21/76844 ,  H01L21/76877 ,  H01L21/76879 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53209 ,  H01L23/53252 ,  H01L23/53266 ,  H01L21/3212

Abstract: Interconnect structures and method of forming the same are disclosed herein. An exemplary interconnect structure includes a first contact feature in a first dielectric layer, a second dielectric layer over the first dielectric layer, a second contact feature over the first contact feature, a barrier layer between the second dielectric layer and the second contact feature, and a liner between the barrier layer and the second contact feature. An interface between the first contact feature and the second contact feature includes the liner but is free of the barrier layer.

公开(公告)号：US11935783B2

公开(公告)日：2024-03-19

申请号：US17745614

申请日：2022-05-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yen Huang ,  Shao-Kuan Lee ,  Cheng-Chin Lee ,  Hai-Ching Chen ,  Shau-Lin Shue

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/76879 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76807 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76856 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/53295

Abstract: Examples of an integrated circuit with an interconnect structure and a method for forming the integrated circuit are provided herein. In some examples, the method includes receiving a workpiece that includes a substrate and an interconnect structure. The interconnect structure includes a first conductive feature disposed within a first inter-level dielectric layer. A blocking layer is selectively formed on the first conductive feature without forming the blocking layer on the first inter-level dielectric layer. An alignment feature is selectively formed on the first inter-level dielectric layer without forming the alignment feature on the blocking layer. The blocking layer is removed from the first conductive feature, and a second inter-level dielectric layer is formed on the alignment feature and on the first conductive feature. The second inter-level dielectric layer is patterned to define a recess for a second conductive feature, and the second conductive feature is formed within the recess.

公开(公告)号：US11929326B2

公开(公告)日：2024-03-12

申请号：US17556134

申请日：2021-12-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shin-Yi Yang ,  Ming-Han Lee ,  Shau-Lin Shue

IPC: H01L23/532 ,  H01L21/324 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L23/53238 ,  H01L21/324 ,  H01L21/76876 ,  H01L23/5226

Abstract: Interconnect structures and method of forming the same are disclosed herein. An exemplary interconnect structure includes a first contact feature in a first dielectric layer, a second dielectric layer over the first dielectric layer, a third dielectric layer over the second dielectric layer, a second contact feature extending through the second dielectric layer and the third dielectric layer, and a graphene layer between the second contact feature and the third dielectric layer.

公开(公告)号：US11860550B2

公开(公告)日：2024-01-02

申请号：US17868398

申请日：2022-07-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tai-I Yang ,  Wei-Chen Chu ,  Hsiang-Wei Liu ,  Shau-Lin Shue ,  Li-Lin Su ,  Yung-Hsu Wu

IPC: G03F7/00 ,  H01L21/768 ,  G03F7/004 ,  G03F7/09

CPC classification number: G03F7/70633 ,  G03F7/0035 ,  G03F7/0043 ,  G03F7/0047 ,  G03F7/094 ,  G03F7/70625 ,  H01L21/7682 ,  H01L21/76807 ,  H01L21/76837 ,  H01L21/76885 ,  H01L21/76897 ,  H01L21/76849

Abstract: Photolithography overlay errors are a source of patterning defects, which contribute to low wafer yield. An interconnect formation process that employs a patterning photolithography/etch process with self-aligned interconnects is disclosed herein. The interconnection formation process, among other things, improves a photolithography overlay (OVL) margin since alignment is accomplished on a wider pattern. In addition, the patterning photolithography/etch process supports multi-metal gap fill and low-k dielectric formation with voids.

公开(公告)号：US11742239B2

公开(公告)日：2023-08-29

申请号：US17501523

申请日：2021-10-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Kang Fu ,  Ming-Han Lee ,  Shau-Lin Shue

IPC: H01L21/768 ,  H01L21/321 ,  H01L23/535 ,  H01L23/532

CPC classification number: H01L21/7684 ,  H01L21/3212 ,  H01L21/76805 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76841 ,  H01L21/76843 ,  H01L21/76895 ,  H01L23/535 ,  H01L23/53209 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252

Abstract: A method of forming a semiconductor structure includes removing a top portion of a conductive feature disposed in a first dielectric layer and over a semiconductor substrate to form a first recess, depositing a second dielectric layer over the first dielectric layer, where the second dielectric layer includes a first region disposed vertically above the first recess and a second region disposed adjacent the first region, and forming a third dielectric layer over the second dielectric layer. The method further includes subsequently forming openings in the third dielectric layer that extend to expose the second dielectric layer, depositing a conductive material in the openings, and planarizing the conductive material to form conductive features in the first and the second regions, where the planarizing completely removes portions of the third dielectric layer disposed in the second region.

公开(公告)号：US20230073811A1

公开(公告)日：2023-03-09

申请号：US17984443

申请日：2022-11-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Ping Chen ,  Yung-Hsu Wu ,  Chia-Tien Wu ,  Min Cao ,  Ming-Han Lee ,  Shau-Lin Shue ,  Shin-Yi Yang

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/528 ,  H01L23/522

Abstract: Interconnect structures and method of forming the same are disclosed herein. An exemplary interconnect structure includes a first contact feature in a first dielectric layer, a second dielectric layer over the first dielectric layer, a second contact feature over the first contact feature, a barrier layer between the second dielectric layer and the second contact feature, and a liner between the barrier layer and the second contact feature. An interface between the first contact feature and the second contact feature includes the liner but is free of the barrier layer.