公开(公告)号：US11145806B2

公开(公告)日：2021-10-12

申请号：US16889395

申请日：2020-06-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Carlos H. Diaz ,  Harry-Hak-Lay Chuang ,  Ru-Liang Lee

IPC: H01L43/02 ,  H01L43/08 ,  H01L27/22 ,  H01L43/12 ,  H01L21/302

Abstract: A device includes a plurality of bottom electrode features, a plurality of Magnetic Tunnel Junction (MTJ) stacks formed on top surfaces of the bottom electrode features, top electrode features formed on top of the MTJ stacks, and an etch stop layer extending along side surfaces of the bottom electrode feature and partially along side surfaces of the MTJ stacks.

公开(公告)号：US11005032B2

公开(公告)日：2021-05-11

申请号：US16711626

申请日：2019-12-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Harry-Hak-Lay Chuang ,  Hung Cho Wang ,  Jiunyu Tsai ,  Sheng-Huang Huang

IPC: G11C11/00 ,  H01L43/02 ,  G11C11/16 ,  H01L43/12

Abstract: Some embodiments relate to a method for manufacturing a magnetoresistive random-access memory (MRAM) cell. The method includes forming a spacer layer surrounding at least a magnetic tunnel junction (MTJ) layer and a top electrode of the MRAM cell; etching the spacer layer to expose a top surface of the top electrode and a top surface of a spacer formed by the spacer layer; forming an upper etch stop layer over the top electrode top surface and the spacer top surface; and forming an upper metal layer in contact with the top electrode top surface of the MRAM cell. A width of the upper etch stop layer is greater than a width of a bottom surface of the upper metal layer.

公开(公告)号：US20210111333A1

公开(公告)日：2021-04-15

申请号：US16601723

申请日：2019-10-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yao-Wen Chang ,  Chung-Chiang Min ,  Harry-Hak-Lay Chuang ,  Hung Cho Wang ,  Tsung-Hsueh Yang ,  Yuan-Tai Tseng ,  Sheng-Huang Huang ,  Chia-Hua Lin

IPC: H01L43/02 ,  H01L27/22 ,  H01L43/12

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip including a magnetoresistive random access memory (MRAM) cell over a substrate. A dielectric structure overlies the substrate. The MRAM cell is disposed within the dielectric structure. The MRAM cell includes a magnetic tunnel junction (MTJ) sandwiched between a bottom electrode and a top electrode. A conductive wire overlies the top electrode. A sidewall spacer structure continuously extends along a sidewall of the MTJ and the top electrode. The sidewall spacer structure includes a first sidewall spacer layer, a second sidewall spacer layer, and a protective sidewall spacer layer sandwiched between the first and second sidewall spacer layers. The first and second sidewall spacer layers comprise a first material and the protective sidewall spacer layer comprises a second material different than the first material.

公开(公告)号：US10957704B2

公开(公告)日：2021-03-23

申请号：US16734691

申请日：2020-01-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Harry-Hak-Lay Chuang ,  Wei Cheng Wu ,  Ya-Chen Kao ,  Yi Hsien Lu

IPC: H01L29/792 ,  H01L27/11573 ,  H01L29/66 ,  H01L29/423 ,  H01L29/51 ,  H01L21/8234 ,  H01L27/092 ,  H01L27/088

Abstract: The present disclosure relates to a structure and method for embedding a non-volatile memory (NVM) in a HKMG (high-κ metal gate) integrated circuit which includes a high-voltage (HV) HKMG transistor. NVM devices (e.g., flash memory) are operated at high voltages for its read and write operations and hence a HV device is necessary for integrated circuits involving non-volatile embedded memory and HKMG logic circuits. Forming a HV HKMG circuit along with the HKMG periphery circuit reduces the need for additional boundaries between the HV transistor and rest of the periphery circuit. This method further helps reduce divot issue and reduce cell size.

公开(公告)号：US20200303629A1

公开(公告)日：2020-09-24

申请号：US16899700

申请日：2020-06-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Harry-Hak-Lay Chuang ,  Hung Cho Wang ,  Tong-Chern Ong ,  Wen-Ting Chu ,  Yu-Wen Liao ,  Kuei-Hung Shen ,  Kuo-Yuan Tu ,  Sheng-Huang Huang

IPC: H01L43/02 ,  H01L45/00 ,  H01L43/12 ,  H01L43/08 ,  H01L43/10

Abstract: The present disclosure relates to an integrated circuit. The integrated circuit includes a an inter-layer dielectric (ILD) structure laterally surrounding a conductive interconnect. A dielectric protection layer is disposed over the ILD structure and a passivation layer is disposed over the dielectric protection layer. The passivation layer includes a protrusion extending outward from an upper surface of the passivation layer. A bottom electrode continuously extends from over the passivation layer to between sidewalls of the passivation layer. A data storage element is over the bottom electrode and a top electrode is over the data storage element.

公开(公告)号：US10686125B2

公开(公告)日：2020-06-16

申请号：US16222031

申请日：2018-12-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Harry-Hak-Lay Chuang ,  Hung Cho Wang ,  Tong-Chern Ong ,  Wen-Ting Chu ,  Yu-Wen Liao ,  Kuei-Hung Shen ,  Kuo-Yuan Tu ,  Sheng-Huang Huang

IPC: H01L47/00 ,  H01L43/02 ,  H01L45/00 ,  H01L43/12 ,  H01L43/08 ,  H01L43/10

Abstract: The present disclosure, in some embodiments, relates to an integrated circuit. The integrated circuit includes a dielectric protection layer disposed over a dielectric structure that laterally surrounds one or more conductive interconnect layers. The dielectric protection layer has a protrusion extending outward from an upper surface of the dielectric protection layer. A bottom electrode is disposed over the dielectric protection layer and has sidewalls extending outward from a lower surface of the bottom electrode through the dielectric protection layer. The bottom electrode has a substantially planar upper surface over the protrusion. A data storage element is over the substantially planar upper surface of the bottom electrode, and a top electrode is over the data storage element.

公开(公告)号：US20200098440A1

公开(公告)日：2020-03-26

申请号：US16410308

申请日：2019-05-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Harry-Hak-Lay Chuang ,  Tien-Wei Chiang ,  Wen-Chun You ,  Yi-Chieh Chiu ,  Yu-Lin Chen ,  Jian-Cheng Huang ,  Chang-Hung Chen

IPC: G11C17/16 ,  G11C17/18 ,  H01L27/22 ,  H01L43/02 ,  H01L43/12

Abstract: Various embodiments of the present application are directed towards a one-time-programmable (OTP) implementation using magnetic junctions. In some embodiments, an array comprises multiple magnetic junctions in multiple columns and multiple rows, and the magnetic junctions comprise a first magnetic junction and a second magnetic junction. The first and second magnetic junctions comprise individual top ferromagnetic elements and individual bottom ferromagnetic elements, and further comprise individual barrier elements between the top and bottom ferromagnetic elements. A first barrier element of the first magnetic junction electrically separates first top and bottom ferromagnetic elements of the first magnetic junction. A second barrier element of the second magnetic junction has undergone breakdown, such that it has defects defining a leakage path between second top and bottom ferromagnetic elements of the second magnetic junction. The broken-down state corresponds to a one-time programmed state and is not susceptible to high-temperature change, even at small sizes.

公开(公告)号：US20200020848A1

公开(公告)日：2020-01-16

申请号：US16580419

申请日：2019-09-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Harry-Hak-Lay Chuang ,  Hung Cho Wang ,  Jiunyu Tsai ,  Sheng-Huang Huang

IPC: H01L43/02 ,  G11C11/16 ,  H01L43/12

Abstract: Some embodiments relate to a method for manufacturing a magnetoresistive random-access memory (MRAM) cell. The method includes forming a spacer layer surrounding at least a magnetic tunnel junction (MTJ) layer and a top electrode of the MRAM cell; etching the spacer layer to expose a top surface of the top electrode and a top surface of a spacer formed by the spacer layer; forming an upper etch stop layer over the top electrode top surface and the spacer top surface; and forming an upper metal layer in contact with the top electrode top surface of the MRAM cell. A width of the upper etch stop layer is greater than a width of a bottom surface of the upper metal layer.

公开(公告)号：US10522740B2

公开(公告)日：2019-12-31

申请号：US15991004

申请日：2018-05-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Harry-Hak-Lay Chuang ,  Hung Cho Wang ,  Jiunyu Tsai ,  Sheng-Huang Huang

IPC: G11C11/00 ,  H01L43/02 ,  G11C11/16 ,  H01L43/12

Abstract: Some embodiments relate to an integrated circuit including a magnetoresistive random-access memory (MRAM) cell. The integrated circuit includes a lower metal layer and an upper metal layer disposed over the lower metal layer. A bottom electrode is disposed over and in electrical contact with the lower metal layer. A magnetic tunneling junction (MTJ) is disposed over an upper surface of bottom electrode. A top electrode is disposed over an upper surface of the MTJ and is in contact with the upper metal layer. A sidewall spacer surrounds an outer periphery of the top electrode. An etch stop layer is disposed on top of an outer periphery of the spacer top surface and surrounding an outer periphery of the bottom surface of the upper metal layer. The etch stop layer overhangs the outer periphery of the spacer top surface.

公开(公告)号：US10516026B2

公开(公告)日：2019-12-24

申请号：US16166603

申请日：2018-10-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chang-Ming Wu ,  Wei Cheng Wu ,  Shih-Chang Liu ,  Harry-Hak-Lay Chuang ,  Chia-Shiung Tsai

IPC: H01L29/423 ,  H01L27/11521 ,  H01L27/1157 ,  H01L27/11524 ,  H01L27/11568 ,  H01L29/66 ,  H01L21/28 ,  H01L29/792 ,  H01L29/51

Abstract: The present disclosure, in some embodiments, relates to a method of forming a memory cell. The method may be performed by forming a select gate on a side of a sacrificial spacer that is disposed over an upper surface of a substrate. The select gate has a non-planar top surface. An inter-gate dielectric layer is formed on the select gate and a memory gate is formed on the inter-gate dielectric layer. The inter-gate dielectric layer extends under the memory gate and defines a recess between sidewalls of the memory gate and select gate. The recess is filled with a first dielectric material.