公开(公告)号：US11765880B2

公开(公告)日：2023-09-19

申请号：US17245912

申请日：2021-04-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yanghee Lee ,  Seokhan Park ,  Sungchang Park ,  Boun Yoon ,  Ilyoung Yoon ,  Youngsuk Lee ,  Junseop Lee ,  Seungho Han ,  Jaeyong Han ,  Jeehwan Heo

IPC: H10B12/00

CPC classification number: H10B12/01

Abstract: A method of manufacturing a semiconductor device includes: forming a lower structure that includes a substrate and conductive lines on the substrate, within a chip region and an edge region of the lower structure; forming data storage structures on the chip region of the lower structure; forming dummy structures on the edge region of the lower structure; forming an interlayer insulating layer covering the data storage structures and the dummy structures on the lower structure, the interlayer insulating layer including high step portions and low step portions, an upper end of the low step portions being lower than an upper end of the high step portions; and planarizing the interlayer insulating layer.

公开(公告)号：US20230030176A1

公开(公告)日：2023-02-02

申请号：US17662316

申请日：2022-05-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yanghee Lee ,  Jonghyuk Park ,  Jinwoo Bae ,  Boun Yoon ,  Ilyoung Yoon

IPC: H01L27/108

Abstract: A semiconductor device may include a substrate including a cell region and a peripheral region, lower electrodes on the cell region of the substrate, a dielectric layer on surfaces of the lower electrodes, a silicon germanium layer on the dielectric layer, a metal plate pattern and a polishing stop layer pattern stacked on the silicon germanium layer, and upper contact plugs physically contacting an upper surface of the silicon germanium layer. The upper contact plugs may have an upper surface farther away from the substrate than an upper surface of the polishing stop layer pattern. The upper contact plugs may be spaced apart from the metal plate pattern and the polishing stop layer pattern.

公开(公告)号：US20220344345A1

公开(公告)日：2022-10-27

申请号：US17859247

申请日：2022-07-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yanghee Lee ,  Jonghyuk Park ,  Ilyoung Yoon ,  Boun Yoon ,  Heesook Cheon

IPC: H01L27/108

Abstract: A semiconductor device includes a substrate including first and second region, a bit line structure on the first region, key structures on the second region, each key structure having an upper surface substantially coplanar with an upper surface of the bit line structure, a first trench disposed between two adjacent key structures spaced apart from each other in a first direction, a filling pattern in a lower portion of the first trench, the filling pattern having a flat upper surface and including a first conductive material, and a first conductive structure on the flat upper surface of the filling pattern, an upper sidewall of the first trench, and the upper surface of each of the plurality of key structures, the first conductive structure including a second conductive material.

公开(公告)号：US11424133B2

公开(公告)日：2022-08-23

申请号：US16825237

申请日：2020-03-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kenji Takai ,  Do Yoon Kim ,  Boun Yoon

IPC: H01L21/321 ,  H01L21/768 ,  H01L21/288 ,  C09G1/04 ,  C09K3/14 ,  B24B37/04

Abstract: A method of manufacturing a metal structure including forming a metal layer including a metal and a nano-abrasive and supplying slurry on the metal layer to perform chemical mechanical polishing, a metal structure including a metal and a nano-abrasive having an average particle diameter of less than about 5 nanometers, and a metal wire, a semiconductor device, and an electronic device including the same.

公开(公告)号：US20220115379A1

公开(公告)日：2022-04-14

申请号：US17245912

申请日：2021-04-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yanghee Lee ,  Seokhan Park ,  Sungchang Park ,  Boun Yoon ,  Ilyoung Yoon ,  Youngsuk Lee ,  Junseop Lee ,  Seungho Han ,  Jaeyong Han ,  Jeehwan Heo

IPC: H01L27/108

Abstract: A method of manufacturing a semiconductor device includes: forming a lower structure that includes a substrate and conductive lines on the substrate, within a chip region and an edge region of the lower structure; forming data storage structures on the chip region of the lower structure; forming dummy structures on the edge region of the lower structure; forming an interlayer insulating layer covering the data storage structures and the dummy structures on the lower structure, the interlayer insulating layer including high step portions and low step portions, an upper end of the low step portions being lower than an upper end of the high step portions; and planarizing the interlayer insulating layer.

公开(公告)号：US11183501B2

公开(公告)日：2021-11-23

申请号：US16819920

申请日：2020-03-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyesung Park ,  Jinwoo Bae ,  Youngho Koh ,  Jonghyuk Park ,  Boun Yoon ,  Myungjae Jang

IPC: H01L27/108

Abstract: A semiconductor device including a substrate having a cell region and a peripheral region; a cell gate structure disposed on the cell region; a first impurity region and a second impurity region, arranged on first and second sides of the cell gate structure in the cell region; a bit line structure disposed on the cell gate structure and connected to the first impurity region; a peripheral gate structure disposed on the peripheral region; a peripheral capping layer disposed on the peripheral region, covering the peripheral gate structure, and having an upper surface at substantially the same level as an upper end of the bit line structure; and a cell contact structure disposed on the second impurity region, and having a conductive barrier and a contact material layer on the conductive barrier, wherein the conductive barrier covers the upper end of the bit line structure.

公开(公告)号：US10535533B2

公开(公告)日：2020-01-14

申请号：US15868544

申请日：2018-01-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yanghee Lee ,  Jonghyuk Park ,  Choongseob Shin ,  Hyojin Oh ,  Boun Yoon ,  Ilyoung Yoon

IPC: H01L23/48 ,  H01L27/108 ,  H01L21/768 ,  H01L25/065 ,  H01L49/02 ,  H01L21/48

Abstract: A semiconductor may include a substrate including a cell array region and a TSV region, an insulation layer disposed on the substrate and having a recess region on the TSV region, a capacitor on the insulation layer of the cell array region, a dummy support pattern disposed on the insulation layer of the TSV region and overlapping the recess region, when viewed in plan, and a TSV electrode penetrating the dummy support pattern and the substrate.

公开(公告)号：US10388537B2

公开(公告)日：2019-08-20

申请号：US15428963

申请日：2017-02-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chae Lyoung Kim ,  Tae-Hong Kim ,  Jung-Min Oh ,  Yungjun Kim ,  Ingi Kim ,  Boun Yoon ,  Hyosan Lee ,  Sol Han

IPC: B08B3/02 ,  H01L21/306 ,  B24B37/20 ,  B24B53/017 ,  H01L21/02 ,  H01L21/67

Abstract: A cleaning apparatus for removing particles from a substrate is provided. The cleaning apparatus includes a first cleaning unit including a first dual nozzle supplying, to a substrate, a first chemical liquid and a first spray including a first liquid dissolving the first chemical liquid, and a second cleaning unit including a second dual nozzle supplying, to the substrate, a second chemical liquid different from the first chemical liquid and a second spray including a second liquid dissolving the second chemical liquid and being the same as the first liquid.

公开(公告)号：US10177160B2

公开(公告)日：2019-01-08

申请号：US15661280

申请日：2017-07-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youngbeom Pyon ,  Kichul Park ,  Inkwon Kim ,  Ki Hoon Jang ,  Byoungho Kwon ,  Sangkyun Kim ,  Boun Yoon

IPC: H01L21/00 ,  H01L23/528 ,  H01L27/112 ,  H01L23/535 ,  H01L27/11551 ,  H01L27/11578 ,  H01L21/768 ,  H01L21/02 ,  H01L23/538

Abstract: A semiconductor device includes a substrate, a peripheral structure, a lower insulating layer, and a stack. The substrate includes a peripheral circuit region and a cell array region. The peripheral structure is on the peripheral circuit region. The lower insulating layer covers the peripheral circuit region and the cell array region and has a protruding portion protruding from a flat portion. The stack is on the lower insulating layer and the cell array region, and includes upper conductive patterns and insulating patterns which are alternately and repeatedly stacked.

公开(公告)号：US09716162B2

公开(公告)日：2017-07-25

申请号：US14697829

申请日：2015-04-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangjine Park ,  Jae-Jik Baek ,  Myunggeun Song ,  Boun Yoon ,  Sukhun Choi ,  Jeongnam Han

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/49

CPC classification number: H01L29/66545 ,  H01L21/0228 ,  H01L21/31051 ,  H01L21/31111 ,  H01L21/76897 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/4983 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851

Abstract: Provided is a semiconductor device including a substrate with an active pattern, a gate electrode crossing the active pattern, and a gate capping pattern on the gate electrode. The gate capping pattern may have a width larger than that of the gate electrode, and the gate capping pattern may include extended portions extending toward the substrate and at least partially covering both sidewalls of the gate electrode.