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    Method of enabling sparse neural networks on memresistive accelerators
    41.
    发明授权
    Method of enabling sparse neural networks on memresistive accelerators 有权

    公开(公告)号：US11816563B2

    公开(公告)日：2023-11-14

    申请号：US16409487

    申请日：2019-05-10

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Titash Rakshit ,  Ryan M. Hatcher ,  Jorge A. Kittl ,  Borna J. Obradovic ,  Engin Ipek

    IPC: G06F11/07 ,  G06F11/10 ,  G06N3/08 ,  G06F17/16

    CPC classification number: G06N3/08 ,  G06F17/16

    Abstract: A method of storing a sparse weight matrix for a trained artificial neural network in a circuit including a series of clusters. The method includes partitioning the sparse weight matrix into at least one first sub-block and at least one second sub-block. The first sub-block includes only zero-value weights and the second sub-block includes non-zero value weights. The method also includes assigning the non-zero value weights in the at least one second sub-block to at least one cluster of the series of clusters of the circuit. The circuit is configured to perform matrix-vector-multiplication (MVM) between the non-zero value weights of the at least one second sub-block and an input vector during an inference process utilizing the artificial neural network. The sub-blocks containing all zero elements are power gated, thereby reducing overall energy consumption for inference.

    Vertical optical via and method of fabrication
    45.
    发明授权
    Vertical optical via and method of fabrication 有权

    公开(公告)号：US10935743B2

    公开(公告)日：2021-03-02

    申请号：US16749908

    申请日：2020-01-22

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Daniel N. Carothers ,  Titash Rakshit

    IPC: G02B6/43 ,  G02B6/36 ,  G02B6/136 ,  G02B6/12 ,  H01S5/026 ,  G02B6/34

    Abstract: A method for providing a vertical optical via for a semiconductor substrate is described. The semiconductor substrate has a front surface and a back side. A hard mask having an aperture therein is formed on the front surface. Part of the semiconductor substrate exposed by the aperture is removed to form a via hole. The via hole has a width not exceeding one hundred micrometers and a bottom. Cladding layer(s) and core layer(s) are provided in the via hole. The core layer(s) have at least a second index of refraction greater than that of the core layer(s). A portion of the semiconductor substrate including the back side is removed to expose a bottom portion of the core layer(s) and a bottom surface of the semiconductor substrate. The vertical optical via includes the cladding and core layers. The vertical optical via extends from the front surface to the bottom surface.

    METHOD OF ENABLING SPARSE NEURAL NETWORKS ON MEMRESISTIVE ACCELERATORS
    49.
    发明申请
    METHOD OF ENABLING SPARSE NEURAL NETWORKS ON MEMRESISTIVE ACCELERATORS 审中-公开

    公开(公告)号：US20200234114A1

    公开(公告)日：2020-07-23

    申请号：US16409487

    申请日：2019-05-10

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Titash Rakshit ,  Ryan M. Hatcher ,  Jorge A. Kittl ,  Borna J. Obradovic ,  Engin Ipek

    IPC: G06N3/08 ,  G06F17/16

    Abstract: A method of storing a sparse weight matrix for a trained artificial neural network in a circuit including a series of clusters. The method includes partitioning the sparse weight matrix into at least one first sub-block and at least one second sub-block. The first sub-block includes only zero-value weights and the second sub-block includes non-zero value weights. The method also includes assigning the non-zero value weights in the at least one second sub-block to at least one cluster of the series of clusters of the circuit. The circuit is configured to perform matrix-vector-multiplication (MVM) between the non-zero value weights of the at least one second sub-block and an input vector during an inference process utilizing the artificial neural network. The sub-blocks containing all zero elements are power gated, thereby reducing overall energy consumption for inference.

    Selectorless 3D stackable memory
    50.
    发明授权
    Selectorless 3D stackable memory 有权

    公开(公告)号：US10585630B2

    公开(公告)日：2020-03-10

    申请号：US15845985

    申请日：2017-12-18

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Titash Rakshit ,  Borna J. Obradovic ,  Ryan M. Hatcher ,  Vladimir Nikitin ,  Dmytro Apalkov

    IPC: H01L21/822 ,  H01L27/22 ,  G06F3/06 ,  H01L27/11578 ,  H01L21/3105 ,  G11C11/16 ,  G11C11/18 ,  H01L43/08

    Abstract: A memory device and method for providing the memory device are described. The memory device includes word lines, a first plurality of bit lines, a second plurality of bit lines and selectorless memory cells. Each selectorless memory cell is coupled with a word line, a first bit line of the first plurality of bit lines and a second bit line of the second plurality of bit lines. The selectorless memory cell includes first and second magnetic junctions. The first and second magnetic junctions are each programmable using a spin-orbit interaction torque. The word line is coupled between the first and second magnetic junctions. The first and second bit lines are coupled with the first and second magnetic junctions, respectively. The selectorless memory cell is selected for a write operation based on voltages in the word line, the first bit line and the second bit line.

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