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    Thin film transistor array panel and method of manufacturing the same
    41.
    发明授权
    Thin film transistor array panel and method of manufacturing the same 有权
    薄膜晶体管阵列面板及其制造方法

    公开(公告)号：US09076691B2

    公开(公告)日：2015-07-07

    申请号：US13875722

    申请日：2013-05-02

    Applicant: Samsung Display Co., Ltd.

    Inventor： Shin Il Choi ,  Sang Gab Kim ,  Su Bin Bae ,  Yu-Gwang Jeong

    IPC: H01L21/00 ,  H01L27/12 ,  H01L27/32

    CPC classification number: H01L27/124 ,  H01L27/1248 ,  H01L27/322 ,  H01L27/3248

    Abstract: A method of manufacturing a thin film transistor array panel includes: a gate insulating layer disposed on a gate electrode, a semiconductor disposed on the gate insulating layer, a source electrode opposite a drain electrode disposed on the semiconductor, a color filter disposed on the gate insulating layer, an overcoat disposed on the color filter and including an inorganic material. A first dry etching is performed using the photosensitive film pattern as a mask to etch the overcoat and provide a preliminary contact hole, through which a portion of the color filter is exposed. A second dry etching is performed using the overcoat as a mask to etch the color filter through the preliminary contact hole and to provide a contact hole, through which a portion of the drain electrode is exposed. A pixel electrode is connected to the drain electrode through the contact hole, on the overcoat.

    Abstract translation: 制造薄膜晶体管阵列面板的方法包括：设置在栅电极上的栅极绝缘层，设置在栅极绝缘层上的半导体，设置在半导体上的漏电极相对的源电极，设置在栅极上的滤色器 绝缘层，设置在滤色器上并包括无机材料的外涂层。 使用感光膜图案作为掩模进行第一干蚀刻，以蚀刻外涂层并提供初步接触孔，滤色片的一部分穿过该预接触孔。 使用外涂层作为掩模进行第二干蚀刻，以通过预接触孔蚀刻滤色器，并提供接触孔，漏电极的一部分暴露在该接触孔中。 像素电极通过外罩上的接触孔连接到漏电极。

    THIN FILM TRANSISTOR ARRAY PANEL AND MANUFACTURING METHOD THEREOF
    42.
    发明申请
    THIN FILM TRANSISTOR ARRAY PANEL AND MANUFACTURING METHOD THEREOF 有权
    薄膜晶体管阵列及其制造方法

    公开(公告)号：US20150072484A1

    公开(公告)日：2015-03-12

    申请号：US14487300

    申请日：2014-09-16

    Applicant: SAMSUNG DISPLAY CO., LTD.

    Inventor： Ji-Young Park ,  Yu-Gwang Jeong ,  Sang Gab Kim ,  Joon Geol Lee

    IPC: H01L27/12 ,  H01L29/66

    CPC classification number: H01L27/1259 ,  G02F1/134363 ,  G02F1/136227 ,  H01L27/124 ,  H01L29/66765 ,  H01L29/78669 ,  H01L29/78678

    Abstract: A thin film transistor array panel includes a substrate, gate lines, each including a gate pad, a gate insulating layer, data lines, each including a data pad connected to a source and drain electrode, a first passivation layer disposed on the data lines and the drain electrode, a first electric field generating electrode, a second passivation layer disposed on the first electric field generating electrode, and a second electric field generating electrode. The gate insulating layer and the first and second passivation layers include a first contact hole exposing a part of the gate pad, the first and second passivation layers include a second contact hole exposing a part of the data pad, and at least one of the first and second contact holes have a positive taper structure having a wider area at an upper side than at a lower side.

    Abstract translation: 薄膜晶体管阵列面板包括基板，栅极线，每个栅极线包括栅极焊盘，栅极绝缘层，数据线，每条数据线包括连接到源极和漏极的数据焊盘，设置在数据线上的第一钝化层和 漏电极，第一电场产生电极，设置在第一电场产生电极上的第二钝化层和第二电场产生电极。 栅极绝缘层和第一和第二钝化层包括暴露栅极焊盘的一部分的第一接触孔，第一和第二钝化层包括暴露数据焊盘的一部分的第二接触孔，以及第一和第二钝化层中的至少一个 并且第二接触孔具有在上侧具有比在下侧更宽的面积的正锥形结构。

    Method for manufacturing a display panel
    43.
    发明授权
    Method for manufacturing a display panel 有权
    显示面板的制造方法

    公开(公告)号：US08975145B2

    公开(公告)日：2015-03-10

    申请号：US14168971

    申请日：2014-01-30

    Applicant: Samsung Display Co., Ltd.

    Inventor： Yu-Gwang Jeong ,  Young-Wook Lee ,  Sang-Gab Kim ,  Woo-Geun Lee ,  Min-Seok Oh ,  Jang-Soo Kim ,  Kap-Soo Yoon ,  Shin-Il Choi ,  Hong-Kee Chin ,  Seung-Ha Choi ,  Seung-Hwan Shim ,  Sung-Hoon Yang ,  Ki-Hun Jeong

    IPC: H01L33/44 ,  H01L27/12 ,  H01L29/66

    CPC classification number: H01L27/127 ,  H01L27/1214 ,  H01L27/1259 ,  H01L27/1288 ,  H01L29/66765

    Abstract: Embodiments of the present invention relate to a thin film transistor and a manufacturing method of a display panel, and include forming a gate line including a gate electrode on a substrate, forming a gate insulating layer on the gate electrode, forming an intrinsic semiconductor on the gate insulating layer, forming an extrinsic semiconductor on the intrinsic semiconductor, forming a data line including a source electrode and a drain electrode on the extrinsic semiconductor, and plasma-treating a portion of the extrinsic semiconductor between the source electrode and the drain electrode to form a protection member and ohmic contacts on respective sides of the protection member. Accordingly, the process for etching the extrinsic semiconductor and forming an inorganic insulating layer for protecting the intrinsic semiconductor may be omitted such that the manufacturing process of the display panel may be simplified, manufacturing cost may be reduced, and productivity may be improved.

    Abstract translation: 本发明的实施例涉及薄膜晶体管和显示面板的制造方法，包括在基板上形成包括栅电极的栅极线，在栅电极上形成栅绝缘层，在栅电极上形成本征半导体 栅极绝缘层，在本征半导体上形成非本征半导体，在外部半导体上形成包括源电极和漏电极的数据线，以及对源电极和漏极之间的非本征半导体的一部分进行等离子体处理，以形成 保护构件和保护构件的相应侧上的欧姆接触。 因此，可以省略用于蚀刻外部半导体和形成用于保护本征半导体的无机绝缘层的工艺，从而可以简化显示面板的制造工艺，可以降低制造成本，并且可以提高生产率。

    Thin film transistor array panel and method of manufacturing the same
    44.
    发明授权
    Thin film transistor array panel and method of manufacturing the same 有权
    薄膜晶体管阵列面板及其制造方法

    公开(公告)号：US08921852B2

    公开(公告)日：2014-12-30

    申请号：US13915342

    申请日：2013-06-11

    Applicant: Samsung Display Co., Ltd.

    Inventor： Shin II Choi ,  Sang Gab Kim ,  Hyang-Shik Kong ,  Su Bin Bae ,  Yu-Gwang Jeong

    IPC: H01L29/417 ,  H01L29/786 ,  H01L29/12 ,  H01L21/77

    CPC classification number: H01L21/77 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1288 ,  H01L29/41733 ,  H01L29/45 ,  H01L29/66969 ,  H01L29/7869

    Abstract: A thin film transistor array panel includes: a substrate, a gate line positioned on the substrate and including a gate electrode, a semiconductor layer positioned on the substrate and including an oxide semiconductor, a data wire layer positioned on the substrate and including a data line crossing the gate line, a source electrode connected to the data line, and a drain electrode facing the source electrode, and a capping layer covering the data wire layer, in which an end of the capping layer is inwardly recessed as compared to an end of the data wire layer.

    Abstract translation: 薄膜晶体管阵列面板包括：衬底，位于衬底上并包括栅电极的栅极线，位于衬底上并包括氧化物半导体的半导体层，位于衬底上的数据线层，包括数据线 与栅极线交叉，连接到数据线的源电极和面对源电极的漏电极和覆盖数据线层的覆盖层，其中封盖层的端部向内凹入，与顶端 数据线层。

    Display substrate and method of manufacturing the same
    48.
    发明授权
    Display substrate and method of manufacturing the same 有权

    公开(公告)号：US10438974B2

    公开(公告)日：2019-10-08

    申请号：US14606986

    申请日：2015-01-27

    Applicant: Samsung Display Co., LTD.

    Inventor： Yu-Gwang Jeong ,  Shin-Il Choi ,  Su-Bin Bae ,  Sung-Hoon Yang

    IPC: H01L27/12 ,  H01L29/417 ,  H01L29/45 ,  H01L29/66 ,  H01L23/532

    Abstract: According to an exemplary embodiment, a display substrate includes a gate metal pattern comprising a gate electrode, an active pattern disposed on the gate pattern and a source metal pattern disposed on the active pattern. The source metal pattern includes a first lower pattern disposed on the active pattern, a second lower pattern disposed on the first lower pattern, a low-resistance metal pattern disposed on the second lower pattern, and an upper pattern disposed on the low-resistance metal pattern. The first lower pattern, the second lower pattern, and the upper pattern each include a material that is the same.

    Transistor array panel and manufacturing method thereof
    50.
    发明授权
    Transistor array panel and manufacturing method thereof 有权

    公开(公告)号：US10170502B2

    公开(公告)日：2019-01-01

    申请号：US15380596

    申请日：2016-12-15

    Applicant: Samsung Display Co., Ltd.

    Inventor： Yu-Gwang Jeong ,  Hyun Min Cho ,  Su Bin Bae ,  Shin Il Choi ,  Sang Gab Kim

    IPC: H01L27/12 ,  H01L29/417 ,  H01L21/311 ,  G02F1/1368 ,  H01L27/32

    Abstract: A transistor array panel is manufactured by a method that reduces or obviates the need for highly selective etching agents or complex processes requiring multiple photomasks to create contact holes. The panel includes: a substrate; a buffer layer positioned on the substrate; a semiconductor layer positioned on the buffer layer; an intermediate insulating layer positioned on the semiconductor layer; and an upper conductive layer positioned on the intermediate insulating layer, wherein the semiconductor layer includes a first contact hole, the intermediate insulating layer includes a second contact hole positioned in an overlapping relationship with the first contact hole, and the upper conductive layer is in contact with a side surface of the semiconductor layer in the first contact hole.

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