公开(公告)号：US07795708B2

公开(公告)日：2010-09-14

申请号：US11445874

申请日：2006-06-02

Applicant: Romney R. Katti

Inventor： Romney R. Katti

IPC: H01L23/552

CPC classification number: H05K9/0075 ,  H01L23/552 ,  H01L24/49 ,  H01L2224/49109 ,  H01L2924/00014 ,  H01L2924/0102 ,  H01L2924/15156 ,  H01L2924/16195 ,  H05K9/0088 ,  H01L2224/45099

Abstract: A magnetic shield is presented. The shield may be used to protect a microelectronic device from stray magnetic fields. The shield includes at least two layers. A first layer includes a magnetic material that may be used to block DC magnetic fields. A second layer includes a conductive material that may be used to block AC magnetic fields. Depending on the type of material that the first and second layers include, a third layer may be inserted in between the first and second layers. The third layer may include a non-conductive material that may be used to ensure that separate eddy current regions form in the first and second layers.

Abstract translation: 提供磁屏蔽。 屏蔽可用于保护微电子器件免受杂散磁场的影响。 屏蔽层至少包括两层。 第一层包括可用于阻挡直流磁场的磁性材料。 第二层包括可用于阻挡交流磁场的导电材料。 根据第一和第二层包括的材料的类型，第三层可以插入在第一层和第二层之间。 第三层可以包括非导电材料，其可用于确保在第一层和第二层中形成单独的涡流区。

公开(公告)号：US07499313B2

公开(公告)日：2009-03-03

申请号：US11446547

申请日：2006-06-02

Applicant: Romney R. Katti

Inventor： Romney R. Katti

IPC: G11C11/00

CPC classification number: G11C7/20 ,  G11C7/02 ,  G11C7/04 ,  G11C11/16 ,  G11C11/1675 ,  G11C11/1695 ,  G11C13/0033 ,  G11C13/0069 ,  G11C16/3431

Abstract: A nonvolatile memory and a method of operating the memory are described. The memory includes memory cells that may each include a magnetoresistive memory bit. The memory includes toggle circuitry for altering the resistive states of memory cells within the memory without changing the logical states of the memory cells. The memory may be toggled to balance resistive decay associated with operating a memory bit under certain conditions or in extreme environments.

Abstract translation: 描述非易失性存储器和操作存储器的方法。 存储器包括可以包括磁阻存储器位的存储器单元。 存储器包括用于改变存储器中的存储器单元的电阻状态而不改变存储器单元的逻辑状态的触发电路。 存储器可以被切换以平衡在某些条件下或在极端环境中与存储器位操作相关联的电阻衰减。

公开(公告)号：US20080151610A1

公开(公告)日：2008-06-26

申请号：US12017308

申请日：2008-01-21

Applicant: Romney R. Katti ,  Theodore Zhu

Inventor： Romney R. Katti ,  Theodore Zhu

IPC: G11C11/00

CPC classification number: G11C14/0081 ,  G11C11/16 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675

Abstract: The semiconductor industry seeks to replace traditional volatile memory devices with improved non-volatile memory devices. The increased demand for a significantly advanced, efficient, and non-volatile data retention technique has driven the development of integrated Giant-Magneto-resistive (GMR) structures. The present teachings relates to integrated latch memory and logic devices and, in particular, concerns a spin dependent logic device that may be integrated with conventional semiconductor-based logic devices to construct high-speed non-volatile static random access memory (SRAM) cells.

Abstract translation: 半导体行业寻求用改进的非易失性存储器件替代传统的易失性存储器件。 对显着高效，高效和非易失性数据保留技术的需求的增加推动了集成的巨磁阻（GMR）结构的发展。 本教导涉及集成的锁存存储器和逻辑器件，并且特别涉及可以与常规的基于半导体的逻辑器件集成以构建高速非易失性静态随机存取存储器（SRAM）单元的自旋相关逻辑器件。

公开(公告)号：US07383626B2

公开(公告)日：2008-06-10

申请号：US11508671

申请日：2006-08-22

Applicant: Daniel L. Baseman ,  Lonny L. Berg ,  Romney R. Katti ,  Daniel S. Reed ,  Gordon A. Shaw ,  Wei D. Z. Zou

Inventor： Daniel L. Baseman ,  Lonny L. Berg ,  Romney R. Katti ,  Daniel S. Reed ,  Gordon A. Shaw ,  Wei D. Z. Zou

IPC: G11B5/127 ,  H04R31/00

CPC classification number: G11C11/16 ,  G11B5/39 ,  H01L43/12 ,  Y10T29/49032 ,  Y10T29/49041 ,  Y10T29/49043 ,  Y10T29/49044 ,  Y10T29/49046 ,  Y10T29/49048 ,  Y10T29/49052 ,  Y10T29/49155

Abstract: In a method of fabricating a giant magnetoresistive (GMR) device a plurality of magnetoresistive device layers is deposited on a first silicon nitride layer formed on a silicon oxide layer. An etch stop is formed on the magnetoresistive device layers, and a second layer of silicon nitride is formed on the etch stop. The magnetoresistive device layers are patterned to define a plurality of magnetic bits having sidewalls. The second silicon nitride layer is patterned to define electrical contact portions on the etch stop in each magnetic bit. The sidewalls of the magnetic bits are covered with a photoresist layer. A reactive ion etch (RIE) process is used to etch into the first silicon nitride and silicon oxide layers to expose electrical contacts. The photoresist layer and silicon nitride layers protect the magnetoresistive layers from exposure to oxygen during the etching into the silicon oxide layer.

Abstract translation: 在制造巨磁阻（GMR）器件的方法中，多个磁阻器件层沉积在形成于氧化硅层上的第一氮化硅层上。 在磁阻器件层上形成蚀刻停止层，在蚀刻停止层上形成第二氮化硅层。 图案化磁阻器件层以限定具有侧壁的多个磁性位。 将第二氮化硅层图案化以限定每个磁头中蚀刻停止点上的电接触部分。 磁头的侧壁被光致抗蚀剂层覆盖。 使用反应离子蚀刻（RIE）工艺来蚀刻到第一氮化硅和氧化硅层中以暴露电触点。 在蚀刻到氧化硅层期间，光致抗蚀剂层和氮化硅层保护磁阻层免受暴露于氧气。

公开(公告)号：US07339818B2

公开(公告)日：2008-03-04

申请号：US11146997

申请日：2005-06-06

Applicant: Romney R. Katti ,  Theodore Zhu

Inventor： Romney R. Katti ,  Theodore Zhu

IPC: G11C11/00

CPC classification number: G11C14/0081 ,  G11C11/16 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675

Abstract: The semiconductor industry seeks to replace traditional volatile memory devices with improved non-volatile memory devices. The increased demand for a significantly advanced, efficient, and non-volatile data retention technique has driven the development of integrated Giant-Magneto-resistive (GMR) structures. The present teachings relates to integrated latch memory and logic devices and, in particular, concerns a spin dependent logic device that may be integrated with conventional semiconductor-based logic devices to construct high-speed non-volatile static random access memory (SRAM) cells.

Abstract translation: 半导体行业寻求用改进的非易失性存储器件替代传统的易失性存储器件。 对显着高效，高效和非易失性数据保留技术的需求的增加推动了集成的巨磁阻（GMR）结构的发展。 本教导涉及集成的锁存存储器和逻辑器件，并且特别涉及可以与常规的基于半导体的逻辑器件集成以构建高速非易失性静态随机存取存储器（SRAM）单元的自旋相关逻辑器件。

公开(公告)号：US20070279970A1

公开(公告)日：2007-12-06

申请号：US11446547

申请日：2006-06-02

Applicant: Romney R. Katti

Inventor： Romney R. Katti

IPC: G11C11/00

CPC classification number: G11C7/20 ,  G11C7/02 ,  G11C7/04 ,  G11C11/16 ,  G11C11/1675 ,  G11C11/1695 ,  G11C13/0033 ,  G11C13/0069 ,  G11C16/3431

Abstract: A nonvolatile memory and a method of operating the memory are described. The memory includes memory cells that may each include a magnetoresistive memory bit. The memory includes toggle circuitry for altering the resistive states of memory cells within the memory without changing the logical states of the memory cells. The memory may be toggled to balance resistive decay associated with operating a memory bit under certain conditions or in extreme environments.

Abstract translation: 描述非易失性存储器和操作存储器的方法。 存储器包括可以包括磁阻存储器位的存储器单元。 存储器包括用于改变存储器中的存储器单元的电阻状态而不改变存储器单元的逻辑状态的触发电路。 存储器可以被切换以平衡在某些条件下或在极端环境中与存储器位操作相关联的电阻衰减。

公开(公告)号：US07193892B2

公开(公告)日：2007-03-20

申请号：US10914327

申请日：2004-08-09

Applicant: Romney R. Katti

Inventor： Romney R. Katti

IPC: G11C11/15

CPC classification number: G11C11/16 ,  G11C11/15

Abstract: A magnetoresistive apparatus and method of operation with improved switching characteristics is provided. Switching of a magnetic direction of a magnetic layer of a magnetoresistive bit is promoted by parallel rotation of local magnetic direction of ends of the bit toward alignment with a hard-axis of the bit. Thus, an embodiment provides for expanded hard-axis magnetic volume of the bit ends to support hard-axis magnetization through bit shape alteration or doping, for example. A method provides for applying a hard-axis magnetic field to the bit ends for initiating switching and applying an easy-axis magnetic field for completing switching.

Abstract translation: 提供了具有改进的开关特性的磁阻装置和操作方法。 通过使位的端部的局部磁方向与钻头的硬轴对齐来促进磁阻位的磁层的磁方向的切换。 因此，实施例提供了位端的扩展的硬轴磁体积，以例如通过钻头形状改变或掺杂来支持硬轴磁化。 一种方法提供将硬轴磁场施加到位端以启动切换并施加易轴磁场以完成切换。

公开(公告)号：US07114240B2

公开(公告)日：2006-10-03

申请号：US10706531

申请日：2003-11-12

Applicant: Daniel L. Baseman ,  Lonny L. Berg ,  Romney R. Katti ,  Daniel S. Reed ,  Gordon A. Shaw ,  Wei D. Z. Zou

Inventor： Daniel L. Baseman ,  Lonny L. Berg ,  Romney R. Katti ,  Daniel S. Reed ,  Gordon A. Shaw ,  Wei D. Z. Zou

IPC: G11B5/127 ,  H04R31/00

CPC classification number: G11C11/16 ,  G11B5/39 ,  H01L43/12 ,  Y10T29/49032 ,  Y10T29/49041 ,  Y10T29/49043 ,  Y10T29/49044 ,  Y10T29/49046 ,  Y10T29/49048 ,  Y10T29/49052 ,  Y10T29/49155

Abstract: In a method of fabricating a giant magnetoresistive (GMR) device a plurality of magnetoresistive device layers is deposited on a first silicon nitride layer formed on a silicon oxide layer. An etch stop is formed on the magnetoresistive device layers, and a second layer of silicon nitride is formed on the etch stop. The magnetoresistive device layers are patterned to define a plurality of magnetic bits having sidewalls. The second silicon nitride layer is patterned to define electrical contact portions on the etch stop in each magnetic bit. The sidewalls of the magnetic bits are covered with a photoresist layer. A reactive ion etch (RIE) process is used to etch into the first silicon nitride and silicon oxide layers to expose electrical contacts. The photoresist layer and silicon nitride layers protect the magnetoresistive layers from exposure to oxygen during the etching into the silicon oxide layer.

Abstract translation: 在制造巨磁阻（GMR）器件的方法中，多个磁阻器件层沉积在形成于氧化硅层上的第一氮化硅层上。 在磁阻器件层上形成蚀刻停止层，在蚀刻停止层上形成第二氮化硅层。 图案化磁阻器件层以限定具有侧壁的多个磁性位。 将第二氮化硅层图案化以限定每个磁头中蚀刻停止点上的电接触部分。 磁头的侧壁被光致抗蚀剂层覆盖。 使用反应离子蚀刻（RIE）工艺来蚀刻到第一氮化硅和氧化硅层中以暴露电触点。 在蚀刻到氧化硅层期间，光致抗蚀剂层和氮化硅层保护磁阻层免受暴露于氧气。

公开(公告)号：US07053429B2

公开(公告)日：2006-05-30

申请号：US10702974

申请日：2003-11-06

Applicant: Romney R. Katti

Inventor： Romney R. Katti

IPC: H01L31/119

CPC classification number: B82Y25/00 ,  G11B5/39 ,  G11C11/16 ,  H01F10/3272 ,  H01F10/3281 ,  H01L43/08

Abstract: A bias-adjusted giant magnetoresistive (GMR) device includes a ferromagnetic reference layer, which has a magnetization that remains relatively fixed when a range of magnetic fields is applied, and a ferromagnetic switching layer, which has a magnetization that can be changed by applying a relatively small magnetic field. In MRAM applications, the switching layer stores data in the form of the particular orientation of its magnetization relative to the magnetization of the reference layer. At least one of the reference and switching layers is split into at least two ferromagnetic layers separated by one or more layers of a nonmagnetic conductor, such that the hysteresis curve of resistance versus applied magnetic field is substantially symmetric about zero applied magnetic field.

公开(公告)号：US06903399B2

公开(公告)日：2005-06-07

申请号：US10760127

申请日：2004-01-16

Applicant: Romney R. Katti ,  Joel A. Drewes ,  Timothy J. Vogt

Inventor： Romney R. Katti ,  Joel A. Drewes ,  Timothy J. Vogt

IPC: G11C11/00 ,  G11C11/15 ,  G11C11/16 ,  H01F10/32 ,  H01L21/8246 ,  H01L27/105 ,  H01L27/22 ,  H01L43/08 ,  H01L43/12 ,  H01L31/119

CPC classification number: H01L27/222 ,  B82Y25/00 ,  G11C11/15 ,  G11C11/16 ,  H01F10/3268 ,  H01F10/3272 ,  H01F10/3281 ,  H01L43/08

Abstract: The invention relates to improving the switching reliability of a magnetic memory cell in a magnetic random access memory (MRAM). Embodiments of the invention add an antiferromagnet to a magnetic memory cell. An antiferromagnetic layer can be formed adjacent to a soft layer in the MRAM on a side of the soft layer that is opposite to a hard layer of the MRAM. One embodiment further includes an additional interlayer of non-antiferromagnetic material between the antiferromagnetic layer and the soft layer.

Abstract translation: 本发明涉及提高磁性随机存取存储器（MRAM）中磁存储单元的开关可靠性。 本发明的实施例将反铁磁体添加到磁存储单元。 可以在与MRAM的硬层相对的软层侧的MRAM中与软层相邻地形成反铁磁性层。 一个实施例还包括在反铁磁层和软层之间的非反铁磁材料的附加中间层。