公开(公告)号：US06522576B2

公开(公告)日：2003-02-18

申请号：US09992213

申请日：2001-11-14

申请人： Yong Lu ,  Theodore Zhu ,  Romney R. Katti

发明人： Yong Lu ,  Theodore Zhu ,  Romney R. Katti

IPC分类号： G11C1100

CPC分类号： G11C11/5607 ,  G11C7/06 ,  G11C11/15

摘要： A low power, high speed magneto-resistive memory is disclosed. The disclosed memory directly senses the resistive state of one or more magneto-resistive memory elements. This allows the memory to be read during a single read cycle, without the need for a word line current. This may substantially increase the speed and reduce the power of the memory.

公开(公告)号：US20080151610A1

公开(公告)日：2008-06-26

申请号：US12017308

申请日：2008-01-21

申请人： Romney R. Katti ,  Theodore Zhu

发明人： Romney R. Katti ,  Theodore Zhu

IPC分类号： G11C11/00

CPC分类号： G11C14/0081 ,  G11C11/16 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675

摘要： The semiconductor industry seeks to replace traditional volatile memory devices with improved non-volatile memory devices. The increased demand for a significantly advanced, efficient, and non-volatile data retention technique has driven the development of integrated Giant-Magneto-resistive (GMR) structures. The present teachings relates to integrated latch memory and logic devices and, in particular, concerns a spin dependent logic device that may be integrated with conventional semiconductor-based logic devices to construct high-speed non-volatile static random access memory (SRAM) cells.

摘要翻译： 半导体行业寻求用改进的非易失性存储器件替代传统的易失性存储器件。 对显着高效，高效和非易失性数据保留技术的需求的增加推动了集成的巨磁阻（GMR）结构的发展。 本教导涉及集成的锁存存储器和逻辑器件，并且特别涉及可以与常规的基于半导体的逻辑器件集成以构建高速非易失性静态随机存取存储器（SRAM）单元的自旋相关逻辑器件。

公开(公告)号：US07339818B2

公开(公告)日：2008-03-04

申请号：US11146997

申请日：2005-06-06

申请人： Romney R. Katti ,  Theodore Zhu

发明人： Romney R. Katti ,  Theodore Zhu

IPC分类号： G11C11/00

CPC分类号： G11C14/0081 ,  G11C11/16 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675

摘要： The semiconductor industry seeks to replace traditional volatile memory devices with improved non-volatile memory devices. The increased demand for a significantly advanced, efficient, and non-volatile data retention technique has driven the development of integrated Giant-Magneto-resistive (GMR) structures. The present teachings relates to integrated latch memory and logic devices and, in particular, concerns a spin dependent logic device that may be integrated with conventional semiconductor-based logic devices to construct high-speed non-volatile static random access memory (SRAM) cells.

摘要翻译： 半导体行业寻求用改进的非易失性存储器件替代传统的易失性存储器件。 对显着高效，高效和非易失性数据保留技术的需求的增加推动了集成的巨磁阻（GMR）结构的发展。 本教导涉及集成的锁存存储器和逻辑器件，并且特别涉及可以与常规的基于半导体的逻辑器件集成以构建高速非易失性静态随机存取存储器（SRAM）单元的自旋相关逻辑器件。

公开(公告)号：US06717194B2

公开(公告)日：2004-04-06

申请号：US09999684

申请日：2001-10-30

申请人： Harry Liu ,  William Larson ,  Lonny Berg ,  Theodore Zhu ,  Shaoping Li ,  Romney R. Katti ,  Yong Lu ,  Anthony Arrott

发明人： Harry Liu ,  William Larson ,  Lonny Berg ,  Theodore Zhu ,  Shaoping Li ,  Romney R. Katti ,  Yong Lu ,  Anthony Arrott

IPC分类号： H01L31119

CPC分类号： H01L43/12 ,  G11C11/15 ,  H01L43/08

摘要： A magnetic bit structure for a magneto-resistive memory is disclosed that has bit ends that are sufficiently large to accommodate a minimum size contact or via hole. By providing such an arrangement, the magnetic bit structure may be fabricated using conventional contact and/or via processing steps. As such, the cost of manufacturing the device may be reduced, and the overall achievable yield may be increased.

摘要翻译： 公开了一种用于磁阻存储器的磁头结构，其具有足够大的位端以适应最小尺寸的接触或通孔。 通过提供这种布置，可以使用常规的接触和/或通孔处理步骤来制造磁头结构。 因此，可以降低制造装置的成本，并且可以提高总体可实现的产量。

公开(公告)号：US06493258B1

公开(公告)日：2002-12-10

申请号：US09618237

申请日：2000-07-18

申请人： Yong Lu ,  Theodore Zhu ,  Romney R. Katti

发明人： Yong Lu ,  Theodore Zhu ,  Romney R. Katti

IPC分类号： G11C1100

CPC分类号： G11C11/5607 ,  G11C7/06 ,  G11C11/15

摘要： A low power, high speed magneto-resistive memory is disclosed. The disclosed memory directly senses the resistive state of one or more magneto-resistive memory elements. This allows the memory to be read during a single read cycle, without the need for a word line current. This may substantially increase the speed and reduce the power of the memory.

公开(公告)号：US20120201076A1

公开(公告)日：2012-08-09

申请号：US13448076

申请日：2012-04-16

申请人： Romney R. Katti ,  Theodore Zhu

发明人： Romney R. Katti ,  Theodore Zhu

IPC分类号： G11C11/16

CPC分类号： G11C14/0081 ,  G11C11/16 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675

摘要： The semiconductor industry seeks to replace traditional volatile memory devices with improved non-volatile memory devices. The increased demand for a significantly advanced, efficient, and non-volatile data retention technique has driven the development of integrated Giant-Magneto-resistive (GMR) structures. The present teachings relates to integrated latch memory and logic devices and, in particular, concerns a spin dependent logic device that may be integrated with conventional semiconductor-based logic devices to construct high-speed non-volatile static random access memory (SRAM) cells.

摘要翻译： 半导体行业寻求用改进的非易失性存储器件替代传统的易失性存储器件。 对显着高效，高效和非易失性数据保留技术的需求的增加推动了集成的巨磁阻（GMR）结构的发展。 本教导涉及集成的锁存存储器和逻辑器件，并且特别涉及可以与常规的基于半导体的逻辑器件集成以构建高速非易失性静态随机存取存储器（SRAM）单元的自旋相关逻辑器件。

公开(公告)号：US08164948B2

公开(公告)日：2012-04-24

申请号：US13193523

申请日：2011-07-28

申请人： Romney R. Katti ,  Theodore Zhu

发明人： Romney R. Katti ,  Theodore Zhu

IPC分类号： G11C11/00

CPC分类号： G11C14/0081 ,  G11C11/16 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675

摘要： The semiconductor industry seeks to replace traditional volatile memory devices with improved non-volatile memory devices. The increased demand for a significantly advanced, efficient, and non-volatile data retention technique has driven the development of integrated Giant-Magneto-resistive (GMR) structures. The present teachings relates to integrated latch memory and logic devices and, in particular, concerns a spin dependent logic device that may be integrated with conventional semiconductor-based logic devices to construct high-speed non-volatile static random access memory (SRAM) cells.

摘要翻译： 半导体行业寻求用改进的非易失性存储器件替代传统的易失性存储器件。 对显着高效，高效和非易失性数据保留技术的需求的增加推动了集成的巨磁阻（GMR）结构的发展。 本教导涉及集成的锁存存储器和逻辑器件，并且特别涉及可以与常规的基于半导体的逻辑器件集成以构建高速非易失性静态随机存取存储器（SRAM）单元的自旋相关逻辑器件。

公开(公告)号：US08004882B2

公开(公告)日：2011-08-23

申请号：US12017308

申请日：2008-01-21

申请人： Romney R. Katti ,  Theodore Zhu

发明人： Romney R. Katti ,  Theodore Zhu

IPC分类号： G11C11/00

CPC分类号： G11C14/0081 ,  G11C11/16 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675

摘要： The semiconductor industry seeks to replace traditional volatile memory devices with improved non-volatile memory devices. The increased demand for a significantly advanced, efficient, and non-volatile data retention technique has driven the development of integrated Giant-Magneto-resistive (GMR) structures. The present teachings relates to integrated latch memory and logic devices and, in particular, concerns a spin dependent logic device that may be integrated with conventional semiconductor-based logic devices to construct high-speed non-volatile static random access memory (SRAM) cells.

摘要翻译： 半导体行业寻求用改进的非易失性存储器件替代传统的易失性存储器件。 对显着高效，高效和非易失性数据保留技术的需求的增加推动了集成的巨磁阻（GMR）结构的发展。 本教导涉及集成的锁存存储器和逻辑器件，并且特别涉及可以与常规的基于半导体的逻辑器件集成以构建高速非易失性静态随机存取存储器（SRAM）单元的自旋相关逻辑器件。

公开(公告)号：US06872997B2

公开(公告)日：2005-03-29

申请号：US10765546

申请日：2004-01-26

申请人： Harry Liu ,  William Larson ,  Lonny Berg ,  Theodore Zhu ,  Shaoping Li ,  Romney R. Katti ,  Yong Lu ,  Anthony Arrott

发明人： Harry Liu ,  William Larson ,  Lonny Berg ,  Theodore Zhu ,  Shaoping Li ,  Romney R. Katti ,  Yong Lu ,  Anthony Arrott

IPC分类号： H01L27/105 ,  G11C11/15 ,  H01L21/8246 ,  H01L43/08 ,  H01L43/12 ,  H01L31/119

CPC分类号： H01L43/12 ,  G11C11/15 ,  H01L43/08

摘要： A magnetic bit structure for a magneto-resistive memory is disclosed that has bit ends that are sufficiently large to accommodate a minimum size contact or via hole. By providing such an arrangement, the magnetic bit structure may be fabricated using conventional contact and/or via processing steps. As such, the cost of manufacturing the device may be reduced, and the overall achievable yield may be increased.

摘要翻译： 公开了一种用于磁阻存储器的磁头结构，其具有足够大的位端以适应最小尺寸的接触或通孔。 通过提供这种布置，可以使用常规的接触和/或通孔处理步骤来制造磁头结构。 因此，可以降低制造装置的成本，并且可以提高总体可实现的产量。

公开(公告)号：US08503224B2

公开(公告)日：2013-08-06

申请号：US13448076

申请日：2012-04-16

申请人： Romney R. Katti ,  Theodore Zhu

发明人： Romney R. Katti ,  Theodore Zhu

IPC分类号： G11C11/00

CPC分类号： G11C14/0081 ,  G11C11/16 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675

摘要： The semiconductor industry seeks to replace traditional volatile memory devices with improved non-volatile memory devices. The increased demand for a significantly advanced, efficient, and non-volatile data retention technique has driven the development of integrated Giant-Magneto-resistive (GMR) structures. The present teachings relates to integrated latch memory and logic devices and, in particular, concerns a spin dependent logic device that may be integrated with conventional semiconductor-based logic devices to construct high-speed non-volatile static random access memory (SRAM) cells.

摘要翻译： 半导体行业寻求用改进的非易失性存储器件替代传统的易失性存储器件。 对显着高效，高效和非易失性数据保留技术的需求的增加推动了集成的巨磁阻（GMR）结构的发展。 本教导涉及集成的锁存存储器和逻辑器件，并且特别涉及可以与常规的基于半导体的逻辑器件集成以构建高速非易失性静态随机存取存储器（SRAM）单元的自旋相关逻辑器件。