公开(公告)号：US10018515B2

公开(公告)日：2018-07-10

申请号：US14856004

申请日：2015-09-16

Applicant: QUALCOMM Incorporated

Inventor： Yanxiang Liu ,  Haining Yang ,  Kern Rim

IPC: G01K7/01 ,  H01L27/092 ,  H01L29/786

CPC classification number: G01K7/015 ,  H01L27/0251 ,  H01L27/0924 ,  H01L29/78606

Abstract: A device includes a source contact, a drain contact, a gate contact, and a body contact. The body contact is electrically coupled to a temperature sensing circuit. The source contact, the drain contact, the gate contact, and the body contact are included in a fin field-effect transistor (finFET).

公开(公告)号：US20170186848A1

公开(公告)日：2017-06-29

申请号：US15189325

申请日：2016-06-22

Applicant: QUALCOMM Incorporated

Inventor： Haining Yang ,  Xiangdong Chen

IPC: H01L29/49 ,  H01L21/28 ,  H01L29/66

CPC classification number: H01L29/4966 ,  H01L21/28088 ,  H01L21/823437 ,  H01L27/0207 ,  H01L27/088 ,  H01L29/32 ,  H01L29/4238 ,  H01L29/66545 ,  H01L29/78

Abstract: Semiconductor devices with wider field gates for reduced gate resistance are disclosed. In one aspect, a semiconductor device is provided that employs a gate. The gate is a conductive line disposed above the semiconductor device to form transistors corresponding to active semiconductor regions. Each active semiconductor region has a corresponding channel region. Portions of the gate disposed over each channel region are active gates, and portions not disposed over the channel region, but that are disposed over field oxide regions, are field gates. A voltage differential between each active gate and a source of each corresponding transistor causes current flow in a channel region when the voltage differential exceeds a threshold voltage. The width of each field gate is a larger width than each active gate. The larger width of the field gates results in reduced gate resistance compared to devices with narrower field gates.

公开(公告)号：US09653466B2

公开(公告)日：2017-05-16

申请号：US14817441

申请日：2015-08-04

Applicant: QUALCOMM Incorporated

Inventor： Haining Yang ,  Yanxiang Liu

IPC: H01L27/088 ,  H01L27/092 ,  H01L29/06 ,  H01L21/8238 ,  H01L21/02 ,  H01L21/265 ,  H01L29/66

CPC classification number: H01L27/0924 ,  H01L21/02164 ,  H01L21/26513 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823892 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/66545 ,  H01L29/6681 ,  H01L29/7845

Abstract: A finFET device according to some examples herein may include an active gate element above an active fin element and a dummy fin element that partially breaks the active gate element. In another example, a dummy gate element adjacent to an active gate element contains a dummy fin element that partially breaks the dummy gate element. In another example, a first dummy fin element partially breaks an active gate element and a second dummy fin element partially breaks a dummy gate element. In another example, the dummy fin element is of the same material as the active fin element. In another example, the dummy fin element partially breaks a gate element but does not extend to the substrate like the active fin element.

公开(公告)号：US09653281B2

公开(公告)日：2017-05-16

申请号：US14746606

申请日：2015-06-22

Applicant: QUALCOMM Incorporated

Inventor： Haining Yang ,  Yanxiang Liu

IPC: H01L27/02 ,  H01L21/02 ,  G05B19/418 ,  H01L27/11 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/84 ,  H01L29/78 ,  H01L27/088 ,  H01L27/092 ,  H01L27/12

CPC classification number: H01L21/02 ,  G05B19/418 ,  G05B2219/45031 ,  H01L21/76895 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0207 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1211 ,  H01L29/785

Abstract: In a particular aspect, an integrated circuit includes a first gate structure coupled to a first fin field effect transistor (FinFET) device. The integrated circuit includes a second gate structure coupled to a second FinFET device. The first gate structure and the second gate structure are separated by a dielectric region. The integrated circuit further includes a metal contact having a first surface that is in contact with the dielectric region, the first gate structure, and the second gate structure.

公开(公告)号：US20160163646A1

公开(公告)日：2016-06-09

申请号：US14670280

申请日：2015-03-26

Applicant: QUALCOMM Incorporated

Inventor： Haining Yang ,  Niladri Narayan Mojumder ,  Stanley Seungchul Song

IPC: H01L23/535 ,  H01L21/768 ,  H01L27/088

CPC classification number: H01L23/535 ,  H01L21/76895 ,  H01L27/0207 ,  H01L27/0886 ,  H01L27/1104 ,  H01L29/41791 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An apparatus includes a first fin of a first transistor and a second fin of a second transistor. The apparatus also include a first contact coupled to the first fin and a second contact coupled to the second fin. The apparatus further includes a strapped contact coupled to the first contact and to the second contact.

Abstract translation: 一种装置包括第一晶体管的第一鳍片和第二晶体管的第二鳍片。 该装置还包括耦合到第一鳍片的第一触点和耦合到第二鳍片的第二触点。 该装置还包括耦合到第一触点和第二触点的绑扎触点。

公开(公告)号：US09029983B2

公开(公告)日：2015-05-12

申请号：US14045604

申请日：2013-10-03

Applicant: QUALCOMM Incorporated

Inventor： Xiangdong Chen ,  Haining Yang

IPC: H01L23/522 ,  H01L27/01 ,  H01L27/06 ,  H01L49/02

CPC classification number: H01L23/5222 ,  H01L23/5228 ,  H01L27/016 ,  H01L27/0629 ,  H01L27/0682 ,  H01L28/20 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In one embodiment, a chip comprises a capacitor and a resistor. The capacitor comprises a first capacitor terminal, a second capacitor terminal, and a dielectric layer between the first and second capacitor terminals. The second capacitor terminal and the resistor are both fabricated from a resistor metal layer.

Abstract translation: 在一个实施例中，芯片包括电容器和电阻器。 电容器包括第一电容器端子，第二电容器端子和第一和第二电容器端子之间的电介质层。 第二电容器端子和电阻器均由电阻器金属层制成。

公开(公告)号：US11901427B2

公开(公告)日：2024-02-13

申请号：US17231284

申请日：2021-04-15

Applicant: QUALCOMM Incorporated

Inventor： Haining Yang ,  Junjing Bao

IPC: H01L29/423 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/40

CPC classification number: H01L29/42372 ,  H01L21/823828 ,  H01L27/092 ,  H01L29/401

Abstract: In an aspect, a semiconductor device includes a gate. The gate includes a first portion that is located on one end of the gate, a second portion that is located on an opposite end of the gate from the first portion, and a third portion that is located in-between the first portion and the second portion. A first cap located on top of the first portion. A second cap located on top of the second portion. The third portion is capless. A gate contact is located on top of the third portion.

公开(公告)号：US20220271162A1

公开(公告)日：2022-08-25

申请号：US17180219

申请日：2021-02-19

Applicant: QUALCOMM Incorporated

Inventor： Bin Yang ,  Xia Li ,  Haining Yang

IPC: H01L29/78 ,  H01L29/161 ,  H01L27/092 ,  H01L29/66 ,  H01L21/8238

Abstract: An exemplary high performance P-type field-effect transistor (PFET) fabricated on a silicon (Si) germanium (Ge)(SiGe) buffer layer with a SiGe source and drain having a Ge percentage higher than a threshold that causes dislocations at a Si substrate interface is disclosed. A source and drain including a Ge percentage above a 45% threshold provide increased compressive strain in the channel for higher performance of the PFET. Dislocations are avoided in the lattices of the source and drain by forming the PFET on a SiGe buffer layer rather than directly on a Si substrate and the SiGe buffer layer has a percentage of Ge less than a percentage of Ge in the source and drain. In one example, a lattice of the buffer layer is relaxed by implanting dislocations at an interface of the buffer layer and the Si substrate and annealing the buffer layer.

公开(公告)号：US20220020665A1

公开(公告)日：2022-01-20

申请号：US16928759

申请日：2020-07-14

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Bin Yang ,  Haining Yang

IPC: H01L23/48 ,  H01L23/522 ,  H01L25/065 ,  H01L23/528 ,  H01L21/762

Abstract: Methods, systems, and devices for double side back-end-of-line (BEOL) metallization for pseudo through-silicon via (pTSV) integration are described. An integrated circuit (IC) may include multiple metallic layers integrated within multiple layers of a multi-dimensional integrated stack (e.g., a three dimensional (3D) integrated stack). By performing a BEOL metallization process, the integrated circuit may implement techniques for 3D vertical chip integration. For example, a first set of layers may be formed during a first portion of a BEOL process and a second portion of the BEOL process may integrate a second set of metallic layers as well as a buried power delivery network (PDN). The metallic layers may form a number of pTSVs and may promote a PDN to experience a reduced PDN IR drop. The PDN may be integrated and the pTSVs may be formed by integrating the metallic layers within a number of dielectric layers.

公开(公告)号：US20210265223A1

公开(公告)日：2021-08-26

申请号：US16798947

申请日：2020-02-24

Applicant: QUALCOMM Incorporated

Inventor： Haining Yang ,  Junjing Bao

IPC: H01L21/8238 ,  H01L27/092 ,  H01L21/762 ,  H01L27/02

Abstract: To prevent short defects between source/drains of transistors of a complementary cell circuit, isolation walls are formed in an isolation region between the source/drains of the transistors prior to growing a P-type epitaxial layer and an N-type epitaxial layer on respective sides of the isolation region. The isolation walls provide a physical barrier to prevent formation of short defects that can otherwise form between the P-type and N-type epitaxial layers. Thus, the isolation walls prevent circuit failures resulting from electrical shorts between source/drain regions of transistors in complementary cell circuits. A width of the isolation region between a P-type transistor and an N-type transistor in a circuit cell layout can be reduced so that a total layout area of the complementary cell circuit can be reduced without reducing product yield. A gate cut may be formed in the dummy gate with a process of forming the isolation walls.