公开(公告)号：US20220328237A1

公开(公告)日：2022-10-13

申请号：US17226744

申请日：2021-04-09

Applicant: QUALCOMM Incorporated

Inventor： Xia LI ,  Bin YANG ,  Haining YANG

IPC: H01F27/29 ,  H01F17/00 ,  H01L49/02 ,  H01F41/04

Abstract: Disclosed is apparatus including a vertical spiral inductor. The vertical spiral inductor may include a plurality of dielectric layers formed on a substrate, a plurality of conductive layers, each of the plurality of conductive layers disposed on each of the plurality of dielectric layers, a plurality of insulating layers, each of the plurality of insulating layers disposed on each of the plurality of conductive layers, wherein each of the plurality of insulating layers separates each of the plurality of dielectric layers. A first spiral coil is arranged in a first plane perpendicular to the substrate, where the first spiral coil is formed of first portions of the plurality of conductive layers and a first set of vias of a plurality of vias, configured to connect the first portions of the plurality of conductive layers.

公开(公告)号：US20220131013A1

公开(公告)日：2022-04-28

申请号：US17077807

申请日：2020-10-22

Applicant: QUALCOMM Incorporated

Inventor： Chenjie TANG ,  Gengming TAO ,  Ye LU ,  Bin YANG ,  Xia LI

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/205 ,  H01L29/423 ,  H01L21/02 ,  H01L29/66

Abstract: Certain aspects of the present disclosure generally relate to a semiconductor device implemented with multiple channels in a gate-all-around (GAA) high-electron-mobility transistor (HEMT) and techniques for fabricating such a device. One example semiconductor device generally includes a substrate; a first gate layer disposed above the substrate; a first barrier layer disposed above the first gate layer; a first channel region disposed above the first barrier layer; a second barrier layer disposed above the first channel region; a second gate layer disposed above the second barrier layer; a third barrier layer disposed above the second gate layer; a second channel region disposed above the third barrier layer; a fourth barrier layer disposed above the second channel region; a source region; and a drain region.

公开(公告)号：US20210183869A1

公开(公告)日：2021-06-17

申请号：US16712063

申请日：2019-12-12

Applicant: QUALCOMM Incorporated

Inventor： Xia LI ,  Haining YANG ,  Bin YANG

IPC: H01L27/11 ,  H01L29/78 ,  G11C11/412 ,  H01L29/66

Abstract: Certain aspects are directed to a static random access memory (SRAM) including an SRAM cell with a pass-gate (PG) transistor having increased threshold voltage to improve the read margin of the SRAM cell. The SRAM generally includes a first SRAM cell having a pull-down (PD) transistor and a PG transistor coupled to the PD transistor. In certain aspects, the SRAM includes a second SRAM cell, the second SRAM cell being adjacent to the first SRAM cell and having a PD transistor and a PG transistor coupled to the PD transistor of the second SRAM cell. The SRAM may also include a gate contact region coupled to a gate region of the PG transistor of the first SRAM cell, wherein at least a portion of the gate contact region is offset from a midpoint between the first SRAM cell and the second SRAM cell.

公开(公告)号：US20210134812A1

公开(公告)日：2021-05-06

申请号：US16669837

申请日：2019-10-31

Applicant: QUALCOMM Incorporated

Inventor： Xia LI ,  Haining YANG ,  Bin YANG

IPC: H01L27/1159 ,  H01L29/51 ,  H01L29/78 ,  H01L21/28 ,  H01L29/66

Abstract: Certain aspects of the present disclosure are directed to a semiconductor device. The semiconductor device generally includes a ferroelectric (FE) semiconductor device having a channel region; a gate oxide; a FE region, wherein the gate oxide is disposed between the FE region and the channel region; a gate region, wherein the FE region is disposed between the gate oxide and the gate region; a first semiconductor region disposed adjacent to the channel region; and a second semiconductor region disposed adjacent to the channel region. The semiconductor device may also include a transistor, wherein a region of the transistor is connected to the gate region, the first semiconductor region, or the second semiconductor region of the FE semiconductor device.

公开(公告)号：US20210098533A1

公开(公告)日：2021-04-01

申请号：US16585216

申请日：2019-09-27

Applicant: QUALCOMM Incorporated

Inventor： Bin YANG ,  Xia LI ,  Gengming TAO

IPC: H01L27/24 ,  H01L45/00

Abstract: Certain aspects of the present disclosure generally relate to a vertical resistive random access memory (RRAM). The vertical RRAM generally includes a planar substrate layer and a plurality of fin-like metal-insulator-metal (MIM) structures extending orthogonally above the substrate layer.

公开(公告)号：US20210036222A1

公开(公告)日：2021-02-04

申请号：US16524639

申请日：2019-07-29

Applicant: QUALCOMM Incorporated

Inventor： Xia LI ,  Bin YANG ,  Gengming TAO

IPC: H01L45/00 ,  H01L27/24

Abstract: Certain aspects of the present disclosure are directed to a resistive random access memory (RRAM). The RRAM generally includes a substrate, an insulator region disposed above the substrate, and a gate region disposed adjacent to at least one lateral surface of the insulator region. The RRAM may also include a first non-insulative region disposed adjacent to a lower surface of the insulator region, and a second non-insulative region disposed adjacent to an upper surface of the insulator region.

公开(公告)号：US20210005545A1

公开(公告)日：2021-01-07

申请号：US16503237

申请日：2019-07-03

Applicant: QUALCOMM Incorporated

Inventor： Kai LIU ,  Xia LI ,  Bin YANG

IPC: H01L23/528 ,  H01L23/522

Abstract: An integrated device that includes a substrate, a third plurality of interconnects formed on a third metal layer, a fourth plurality of interconnects formed on a fourth metal layer, at least one dielectric layer formed over the substrate. The third metal layer is located over the substrate. The third metal layer has a third pattern density. The third plurality of interconnects has a third thickness that is approximately the same for all interconnects of the third plurality of interconnects. The fourth metal layer is located over the third metal layer. The fourth metal layer has a fourth pattern density. The fourth pattern density is different than the third pattern density. The fourth plurality of interconnects has a fourth thickness that is approximately the same for all interconnects of the fourth plurality of interconnects.

公开(公告)号：US20190386154A1

公开(公告)日：2019-12-19

申请号：US16007575

申请日：2018-06-13

Applicant: QUALCOMM Incorporated

Inventor： Gengming TAO ,  Xia LI ,  Bin YANG ,  Qingqing LIANG ,  Francesco CAROBOLANTE

IPC: H01L29/93 ,  H01L29/20 ,  H01L29/36 ,  H01L29/66

Abstract: A variable capacitor includes a mesa on a substrate. The mesa has multiple III-V semiconductor layers and includes a first side and a second side opposite the first side. The first side has a first sloped portion and a first horizontal portion. The second side has a second sloped portion and a second horizontal portion. A control terminal is on a third side of the mesa. A first terminal is on the first side of the mesa. The first terminal is disposed on the first horizontal portion and the first sloped portion. A second terminal is also on the substrate.

公开(公告)号：US20190103320A1

公开(公告)日：2019-04-04

申请号：US15723224

申请日：2017-10-03

Applicant: QUALCOMM Incorporated

Inventor： Lixin GE ,  Bin YANG ,  Ye LU ,  Junjing BAO ,  Periannan CHIDAMBARAM

IPC: H01L21/8234 ,  H01L27/06 ,  H01L23/522

Abstract: Middle-of-line (MOL) shielded gate in integrated circuits (ICs) are disclosed. One or more metal resistors are fabricated in a MOL layer in the IC to reduce gate to drain parasitic capacitance in the semiconductor area. By fabricating a metal resistor in the MOL layer, the metal resistor can be localized close to semiconductor devices to more effectively reduce parasitic capacitance of the semiconductor devices without adding costs or defects to the current fabrication processes. The current fabrication processes may be used to create contacts in the MOL to fabricate the metal resistor.

公开(公告)号：US20190027554A1

公开(公告)日：2019-01-24

申请号：US15816295

申请日：2017-11-17

Applicant: QUALCOMM Incorporated

Inventor： Ye LU ,  Yun YUE ,  Phanikumar KONKAPAKA ,  Bin YANG ,  Chuan-Hsing CHEN

IPC: H01L29/06 ,  H01L23/522

Abstract: A metal-oxide-semiconductor (MOS) device for radio frequency (RF) applications may include a guard ring. The guard ring may surround the MOS device and at least one other MOS device. The MOS device may further include a level zero contact layer coupled to a first interconnect layer through level zero interconnects and vias. The first interconnect layer may be for routing to the MOS device.