公开(公告)号：US09633706B1

公开(公告)日：2017-04-25

申请号：US15289495

申请日：2016-10-10

Applicant: QUALCOMM Incorporated

Inventor： Sungryul Kim ,  Jung Pill Kim ,  Hyunsuk Shin

IPC: G11C11/14 ,  G11C11/16

CPC classification number: G11C11/1657 ,  G11C8/08 ,  G11C8/10 ,  G11C8/18 ,  G11C11/1653 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/1693 ,  G11C11/1697

Abstract: A voltage self-boosting circuit for generating a boosted voltage for driving a word line write in a memory array for a memory write operation is provided. A voltage generation circuit(s) is configured to generate a read voltage for a memory read operation and a write voltage for a memory write operation based on a predefined supply voltage. For the memory write operation, a delay circuit delays the delay circuit enable signal by a predetermined delay to generate the output voltage control signal. Accordingly, the voltage generation circuit(s) generates boosted voltage that drives the write voltage to a selected word line(s). For the memory read operation, the voltage generation circuit(s) does not generate the boosted voltage and thus drives the read voltage to the selected word line(s). Hence, it is possible to reduce power consumption and timing delay during the memory read operation or the memory write operation.

公开(公告)号：US09431129B2

公开(公告)日：2016-08-30

申请号：US14266326

申请日：2014-04-30

Applicant: QUALCOMM Incorporated

Inventor： Jung Pill Kim ,  Taehyun Kim ,  Sungryul Kim ,  Xiangyu Dong

IPC: G11C29/02 ,  G11C29/30 ,  G11C7/10 ,  G11C16/26 ,  G11C16/30 ,  G11C14/00 ,  G06F11/10 ,  G11C29/52 ,  G11C7/06 ,  G11C7/08 ,  G11C29/04 ,  G11C11/16 ,  G11C13/00

CPC classification number: G11C29/026 ,  G06F11/106 ,  G06F11/1072 ,  G06F11/1076 ,  G11C7/06 ,  G11C7/08 ,  G11C7/1006 ,  G11C7/1072 ,  G11C11/16 ,  G11C11/1673 ,  G11C13/004 ,  G11C14/0081 ,  G11C14/009 ,  G11C16/26 ,  G11C16/30 ,  G11C29/30 ,  G11C29/52 ,  G11C2029/0411

Abstract: A device includes a plurality of memory cells of a memory array, a sense amplifier of the memory array, and selection logic of the memory array. The sense amplifier is configured to sense at least one data value from at least one memory cell of the plurality of memory cells. The selection logic is configured to select between causing the sense amplifier to sense the at least one data value using a first sensing delay and causing the sense amplifier to sense the at least one data value using a second sensing delay. The second sensing delay is longer than the first sensing delay.

Abstract translation: 一种器件包括存储器阵列的多个存储单元，存储器阵列的读出放大器和存储器阵列的选择逻辑。 感测放大器被配置为感测来自多个存储器单元中的至少一个存储单元的至少一个数据值。 选择逻辑被配置为在使感测放大器使用第一感测延迟来感测至少一个数据值并且使得感测放大器使用第二感测延迟来感测至少一个数据值之间进行选择。 第二感测延迟比第一感测延迟更长。

公开(公告)号：US20160246608A1

公开(公告)日：2016-08-25

申请号：US14627318

申请日：2015-02-20

Applicant: QUALCOMM Incorporated

Inventor： Adam Edward Newham ,  Rashid Ahmed Akbar Attar ,  Seung Hyuk Kang ,  Jung Pill Kim ,  Sungryul Kim ,  Taehyun Kim

IPC: G06F9/44 ,  G06F13/28 ,  G06F12/02

CPC classification number: G06F13/28 ,  G06F9/4406 ,  G06F12/0246 ,  G06F2212/7209

Abstract: Multi-step programming of heat-sensitive non-volatile memory (NVM) in processor-based systems, and related methods and systems are disclosed. To avoid relying on programmed instructions stored in heat-sensitive NVM during fabrication, wherein the programmed instructions can become corrupted during thermal packaging processes, the NVM is programmed in a multi-step programming process. In a first programming step, a boot loader comprising programming instructions is loaded into the NVM. The boot loader may be loaded into the NVM after the thermal processes during packaging are completed to avoid risking data corruption in the boot loader. Thereafter, the programmed image can be loaded quickly into a NV program memory over the peripheral interface using the boot loader to save programming time and associated costs, as opposed to loading the programmed image using lower transfer rate programming techniques. The processor can execute the program instructions to carry out tasks in the processor-based system.

Abstract translation: 公开了基于处理器的系统中的热敏非易失性存储器（NVM）的多步编程以及相关的方法和系统。 为了避免在制造期间依赖于存储在热敏NVM中的编程指令，其中编程指令可能在热封装过程中被破坏，NVM以多步编程过程编程。 在第一编程步骤中，包括编程指令的引导加载器被加载到NVM中。 引导加载程序可能在打包完成后的热处理后加载到NVM中，以避免引导加载程序中的数据损坏风险。 此后，与使用较低传输速率编程技术加载编程图像相比，编程图像可以使用引导加载程序通过外设接口快速加载到NV程序存储器中，从而节省编程时间和相关成本。 处理器可以执行程序指令以在基于处理器的系统中执行任务。

公开(公告)号：US09140747B2

公开(公告)日：2015-09-22

申请号：US13947144

申请日：2013-07-22

Applicant: QUALCOMM Incorporated

Inventor： Jung Pill Kim ,  Taehyun Kim ,  Sungryul Kim ,  Daeik D. Kim

IPC: G11C7/00 ,  G01R31/28 ,  G11C29/14 ,  G11C29/44 ,  G11C29/46 ,  G11C16/28 ,  G11C29/02

CPC classification number: G01R31/2851 ,  G11C16/28 ,  G11C29/02 ,  G11C29/026 ,  G11C29/028 ,  G11C29/14 ,  G11C29/44 ,  G11C29/46

Abstract: A circuit includes a plurality of transistors responsive to a plurality of latches that store a test code. The circuit further includes a first bit line coupled to a data cell and coupled to a sense amplifier. The circuit also includes a second bit line coupled to a reference cell and coupled to the sense amplifier. A current from a set of the plurality of transistors is applied to the data cell via the first bit line. The set of the plurality of transistors is determined based on the test code. The circuit also includes a test mode reference circuit coupled to the first bit line and to the second bit line.

Abstract translation: 电路包括响应于存储测试码的多个锁存器的多个晶体管。 电路还包括耦合到数据单元并耦合到读出放大器的第一位线。 电路还包括耦合到参考单元并耦合到读出放大器的第二位线。 来自一组多个晶体管的电流经由第一位线被施加到数据单元。 基于测试代码来确定多个晶体管的集合。 电路还包括耦合到第一位线和第二位线的测试模式参考电路。

公开(公告)号：US09135975B2

公开(公告)日：2015-09-15

申请号：US14064959

申请日：2013-10-28

Applicant: QUALCOMM Incorporated

Inventor： Taehyun Kim ,  Jung Pill Kim ,  Sungryul Kim

IPC: G11C11/16 ,  G11C29/54 ,  G11C13/00 ,  G11C29/02 ,  G11C29/24

CPC classification number: G11C11/1675 ,  G11C11/1677 ,  G11C13/0002 ,  G11C13/0069 ,  G11C29/021 ,  G11C29/023 ,  G11C29/028 ,  G11C29/24 ,  G11C2013/0083 ,  G11C2013/0092

Abstract: A resistive memory array includes a controller, a test reset driver coupled to the controller, a test write driver also coupled to the controller, and a test read sense amplifier also coupled to the controller. The resistive memory array also includes a set of test resistive memory elements representing a resistive memory macro. The test resistive memory elements are coupled to the test reset driver, the test write driver and the test read sense amplifier. A change in the state of one of the test resistive memory elements represents a change in the state of a set of corresponding elements in the resistive memory macro.

Abstract translation: 电阻性存储器阵列包括控制器，耦合到控制器的测试复位驱动器，还耦合到控制器的测试写入驱动器，以及还耦合到控制器的测试读取读出放大器。 电阻存储器阵列还包括表示电阻存储器宏的一组测试电阻存储器元件。 测试电阻存储元件耦合到测试复位驱动器，测试写驱动器和测试读读放大器。 一个测试电阻存储器元件的状态的变化表示电阻存储器宏中一组相应元件的状态的变化。

公开(公告)号：US08913450B2

公开(公告)日：2014-12-16

申请号：US13680361

申请日：2012-11-19

Applicant: QUALCOMM Incorporated

Inventor： Jung Pill Kim ,  Taehyun Kim ,  Sungryul Kim

IPC: G11C7/00 ,  G11C7/20 ,  G11C16/20 ,  G11C29/00 ,  G11C29/44

CPC classification number: G11C7/20 ,  G11C16/20 ,  G11C29/44 ,  G11C29/789 ,  G11C2029/4402

Abstract: A memory device is provided including a cell array and a volatile storage device. The cell array may include a plurality of word lines, a plurality of bit lines, wherein a selection of a word line and bit line defines a memory cell address, and a non-volatile reserved word line for storing configuration information for the cell array. The volatile storage device is coupled to the cell array. The configuration information from the non-volatile reserved word line is copied to the volatile storage device upon power-up or initialization of the memory device.

Abstract translation: 提供了包括单元阵列和易失性存储装置的存储装置。 单元阵列可以包括多个字线，多个位线，其中字线和位线的选择定义存储器单元地址，以及用于存储单元阵列的配置信息的非易失性保留字线。 易失性存储设备耦合到单元阵列。 来自非易失性保留字线的配置信息在上电或初始化存储器件时被复制到易失性存储设备。