公开(公告)号：US07416104B2

公开(公告)日：2008-08-26

申请号：US11409232

申请日：2006-04-21

Applicant: Steven A. Cordes ,  Peter A. Gruber ,  John U. Knickerbocker ,  James L. Speidell

Inventor： Steven A. Cordes ,  Peter A. Gruber ,  John U. Knickerbocker ,  James L. Speidell

IPC: B23K31/02

CPC classification number: B23K3/0638 ,  B23K35/02 ,  B23K2101/40 ,  H01L2224/11

Abstract: A system and method for injection molding conductive bonding material into a plurality of cavities in a non-rectangular mold is disclosed. The method comprises aligning a fill head with a non-rectangular mold. The non-rectangular mold includes a plurality of cavities. The fill head is placed in substantial contact with the non-rectangular mold. Rotational motion is provided to at least one of the non-rectangular mold and the fill head while the fill head is in substantial contact with the non-rectangular mold. Conductive bonding material is forced out of the fill head toward the non-rectangular mold. The conductive bonding material is provided into at least one cavity of the plurality of cavities contemporaneous with the at least one cavity being in proximity to the fill head.

Abstract translation: 公开了一种用于将导电接合材料注射成非矩形模具中的多个空腔的系统和方法。 该方法包括将填充头与非矩形模具对准。 非矩形模具包括多个空腔。 填充头被放置成与非矩形模具基本接触。 旋转运动提供给非矩形模具和填充头中的至少一个，同时填充头基本上与非矩形模具接触。 将导电接合材料从填充头推向非矩形模具。 导电接合材料被提供到与填充头附近的至少一个空腔同时的多个空腔的至少一个空腔中。

公开(公告)号：US20080179755A1

公开(公告)日：2008-07-31

申请号：US11669924

申请日：2007-01-31

Applicant: Paul S. Andry ,  L. Paivikki Buchwalter ,  Anurag Jain ,  John U. Knickerbocker ,  Edmund J. Sprogis ,  Michelle L. Steen ,  Cornelia K. Tsang

Inventor： Paul S. Andry ,  L. Paivikki Buchwalter ,  Anurag Jain ,  John U. Knickerbocker ,  Edmund J. Sprogis ,  Michelle L. Steen ,  Cornelia K. Tsang

IPC: H01L23/48 ,  H01L21/4763

CPC classification number: H01L23/49827 ,  H01L21/486 ,  H01L21/76898 ,  H01L23/147 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A process and structure for enabling the creation of reliable electrical through-via connections in a semiconductor substrate and a process for filling vias. Problems associated with under etch, over etch and flaring of deep Si RIE etched through-vias are mitigated, thereby vastly improving the integrity of the insulation and metallization layers used to convert the through-vias into highly conductive pathways across the Si wafer thickness. By using an insulating collar structure in the substrate in one case and by filling the via in accordance with the invention in another case, whole wafer yield of electrically conductive through vias is greatly enhanced.

Abstract translation: 一种用于在半导体衬底中创建可靠的电通孔连接的工艺和结构以及用于填充过孔的工艺。 与深蚀刻Si RIE蚀刻通孔相切的蚀刻，过蚀刻和扩散相关的问题得到缓解，从而大大提高了用于将通孔转换成穿过Si晶片厚度的高导电通路的绝缘层和金属化层的完整性。 通过在一种情况下通过在衬底中使用绝缘套环结构，并且在另一种情况下通过填充根据本发明的通孔，大大增强了导电通孔的整个晶片产量。

公开(公告)号：US20080175939A1

公开(公告)日：2008-07-24

申请号：US11930269

申请日：2007-10-31

Applicant: David H. Danovitch ,  Mukta G. Farooq ,  Peter A. Gruber ,  John U. Knickerbocker ,  George R. Proto ,  Da-Yuan Shih

Inventor： David H. Danovitch ,  Mukta G. Farooq ,  Peter A. Gruber ,  John U. Knickerbocker ,  George R. Proto ,  Da-Yuan Shih

IPC: B29C35/08

CPC classification number: H01L24/11 ,  H01L21/6835 ,  H01L24/13 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L24/94 ,  H01L25/0657 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/11003 ,  H01L2224/111 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/27334 ,  H01L2224/73104 ,  H01L2224/83 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2224/27 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A method for forming interconnects onto attachment points of a wafer includes the steps of providing a mold with a plurality of cavities having a predetermined shape, depositing a release agent on surfaces of the cavities, filling the cavities with an interconnect material to form the interconnects, removing the release agent from the mold, and attaching the interconnects to the attachment points of the wafer. An adhesive layer can optionally be deposited in addition to the release layer. The adhesive layer can be used, for example, to bond the chip to a package.

Abstract translation: 用于在晶片的附接点上形成互连的方法包括以下步骤：提供具有预定形状的多个空腔的模具，在空腔的表面上沉积脱模剂，用互连材料填充空腔以形成互连， 从模具中除去脱模剂，以及将互连件附接到晶片的附接点。 除了剥离层之外，还可任选地沉积粘合剂层。 粘合剂层可以用于例如将芯片粘合到包装上。

公开(公告)号：US20080157405A1

公开(公告)日：2008-07-03

申请号：US11619265

申请日：2007-01-03

Applicant: John U. Knickerbocker

Inventor： John U. Knickerbocker

IPC: H01L23/544 ,  H01L21/50

CPC classification number: H01L25/0657 ,  H01L24/75 ,  H01L24/81 ,  H01L25/50 ,  H01L2224/16145 ,  H01L2224/75 ,  H01L2224/757 ,  H01L2224/81121 ,  H01L2224/81801 ,  H01L2225/06513 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2224/0401

Abstract: A method for fabricating a device adapted for precision aligning integrated circuits having small-scale architecture in a stack, the method includes obtaining dimensions of the integrated circuits; fabricating a precision guide using the dimensions; and fabricating alignment fiducials into at least one of the precision guide and a carrier wafer. A method for placing integrated circuits having small-scale architecture into a stack, the method includes selecting a device adapted for precision aligning the integrated circuits into the stack and precision aligning the integrated circuits into the stack.

Abstract translation: 一种用于制造适于在堆叠中精确对准具有小规模架构的集成电路的装置的方法，所述方法包括获得集成电路的尺寸; 使用尺寸制造精密导轨; 以及将对准基准制成精密引导件和载体晶片中的至少一个。 一种用于将具有小规模架构的集成电路放置到堆叠中的方法，所述方法包括选择适于将集成电路精确地对准到堆叠中并将集成电路精确对准到堆叠中的装置。

公开(公告)号：US20070290315A1

公开(公告)日：2007-12-20

申请号：US11538567

申请日：2006-10-04

Applicant: Philip G. Emma ,  John U. Knickerbocker ,  Cirag S. Patel

Inventor： Philip G. Emma ,  John U. Knickerbocker ,  Cirag S. Patel

IPC: H01L23/02

CPC classification number: H01L25/0657 ,  H01L23/642 ,  H01L25/0652 ,  H01L25/18 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2225/06589 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/00

Abstract: A computer chip is structured to have at least one single-layered chip, at least one multi-layered chip stack, and a carrier package characterized by electrical interconnections of less than 100 microns diameter, wherein the single-layered chip and the multi-layered chip stack are each electrically coupled to the electrical interconnections of the carrier package, and the single-layered chip is communicatively coupled to the multi-layered chip stack through the carrier package so that an electrical signal propagates over a given distance between the single-layered chip and the multi-layered chip stack at substantially a speed of propagation for a single layer chip over the given distance. The single-layered chip can be a processor having multi-cores and the multi-layered chip stack can be a memory cache stack. Interconnect vias, having a density at least as great as 2500 interconnects/cm2 electrically couple the single-layered chip and the multi-layered chip stack to the carrier package.

Abstract translation: 计算机芯片被构造成具有至少一个单层芯片，至少一个多层芯片堆叠和以小于100微米直径的电互连为特征的载体封装，其中单层芯片和多层芯片 芯片堆叠都电耦合到载体封装的电互连，并且单层芯片通过载体封装通信地耦合到多层芯片堆叠，使得电信号在单层之间传递给定距离 芯片和多层芯片堆栈，在给定距离内的单层芯片基本上是传播速度。 单层芯片可以是具有多核的处理器，并且多层芯片堆栈可以是存储器高速缓存堆栈。 具有至少高达2500个互连/ cm 2的密度的互连通孔将单层芯片和多层芯片堆叠电耦合到载体封装。

公开(公告)号：US07148566B2

公开(公告)日：2006-12-12

申请号：US09817843

申请日：2001-03-26

Applicant: John U. Knickerbocker ,  Voya R. Markovich ,  Thomas R. Miller ,  William J. Rudik

Inventor： John U. Knickerbocker ,  Voya R. Markovich ,  Thomas R. Miller ,  William J. Rudik

IPC: H01L21/44

CPC classification number: H05K1/0271 ,  H01L23/49866 ,  H01L2924/0002 ,  H05K1/111 ,  H05K3/384 ,  H05K3/4092 ,  H05K2201/0133 ,  H05K2201/0355 ,  H05K2203/0307 ,  H05K2203/1152 ,  H01L2924/00

Abstract: Ball Grid Array packages having decreased adhesion of the BGA pad to the laminate surface and methods for producing same are provided.

公开(公告)号：US06819813B2

公开(公告)日：2004-11-16

申请号：US10242152

申请日：2002-09-11

Applicant: Stephen R. Howland ,  John U. Knickerbocker ,  Steven P. Ostrander ,  Martin L. Schmatz

Inventor： Stephen R. Howland ,  John U. Knickerbocker ,  Steven P. Ostrander ,  Martin L. Schmatz

IPC: G02B612

CPC classification number: G02B6/43 ,  G02B6/12002 ,  G02B6/4204

Abstract: An apparatus for integrating optical devices between a module and a circuit board comprising a carrier having optical waveguides, a module having optical ports on a surface of the module, the surface of the module connected to the carrier such that the optical waveguides are in communication with the optical ports; and a circuit board having optical ports on a surface of the circuit board, the surface of the circuit board connected to the carrier such that the optical waveguides are in communication with the optical ports. The apparatus may also integrate electrical ports on the surface of the module, the surface of the circuit board, and electrical connections on the carrier. The apparatus may also integrate circuit chips having optical ports for communication with the optical waveguides.

公开(公告)号：US06793407B2

公开(公告)日：2004-09-21

申请号：US10254955

申请日：2002-09-25

Applicant: Lawrence Jacobowitz ,  John U. Knickerbocker ,  Ronald P. Luijten ,  Subhash L. Shinde

Inventor： Lawrence Jacobowitz ,  John U. Knickerbocker ,  Ronald P. Luijten ,  Subhash L. Shinde

IPC: G02B626

CPC classification number: G02B6/43 ,  G02B6/4228 ,  G02B6/4249

Abstract: A set of interlocking modules supports and connects a die containing lasers, a set of precision molded lenses and a set of beam switching elements. Another embodiment of the invention is a structure for mounting a logic chip and an optical chip on a chip carrier, with the optical chip being mounted on the side of the carrier facing the system board on which the carrier is mounted, so that radiation travels in a straight path from optical sources on the optical chip into optical transmission guides on the board.

Abstract translation: 一组互锁模块支持并连接包含激光的模具，一组精密模制透镜和一组光束开关元件。 本发明的另一个实施例是用于将芯片和光学芯片安装在芯片载体上的结构，其中光学芯片被安装在载体侧面的载体侧面上，使得辐射在 从光学芯片上的光源到板上的光传输引导件的直线路径。

公开(公告)号：US06657313B1

公开(公告)日：2003-12-02

申请号：US09233385

申请日：1999-01-19

Applicant: Peter J. Brofman ,  Shaji Faroon ,  John U. Knickerbocker ,  Scott I. Langenthal ,  Sudipta K. Ray ,  Kathleen A. Stalter

Inventor： Peter J. Brofman ,  Shaji Faroon ,  John U. Knickerbocker ,  Scott I. Langenthal ,  Sudipta K. Ray ,  Kathleen A. Stalter

IPC: H01L2348

CPC classification number: H05K3/3436 ,  H01L23/49827 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/09701 ,  H05K2201/10378 ,  H05K2201/10424 ,  H05K2201/10674 ,  H05K2203/0415 ,  Y02P70/613 ,  Y10T29/49144 ,  Y10T29/49149 ,  H01L2224/05599

Abstract: A device for preventing short circuits between solder joints in flip chip packaging. The dielectric interposer has a plurality of apertures or vias which correspond to the I/O pads on a chip and substrate. Preferably, the interposer comprises a polyester film, glass, alumina, polyimide, a heat curable polymer or an inorganic powder filler in an organic material. More preferably, the interposer contains an adhesive or has adhesive layers disposed on the linear surfaces of the interposer. Cone shaped solder elements are formed within the apertures of the interposer. The dielectric interposer is positioned between a chip and substrate in an electronic module and thermally reflowed to create an electrical and mechanical interconnection. The interposer prohibits contact between the solder joints by isolating each of the joints and corresponding bonding pads. The interposer also prevents over compression of the solder joints by acting as a stand off.

Abstract translation: 一种用于防止倒装芯片封装中焊点之间短路的装置。 电介质插入件具有与芯片和基板上的I / O焊盘对应的多个孔或通孔。 优选地，中间层包括有机材料中的聚酯膜，玻璃，氧化铝，聚酰亚胺，可热固化聚合物或无机粉末填料。 更优选地，插入件包含粘合剂或者具有设置在插入件的线性表面上的粘合剂层。 锥形焊料元件形成在插入件的孔内。 电介质插入件位于电子模块中的芯片和衬底之间并被热回流以产生电气和机械互连。 插入器通过隔离每个接头和相应的接合焊盘来禁止焊点之间的接触。 插入器还通过作为支架来防止焊点的过度压缩。

公开(公告)号：US06509687B1

公开(公告)日：2003-01-21

申请号：US09450530

申请日：1999-11-30

Applicant: Govindarajan Natarajan ,  Raschid J. Bezama ,  John U. Knickerbocker ,  Robert W. Pasco

Inventor： Govindarajan Natarajan ,  Raschid J. Bezama ,  John U. Knickerbocker ,  Robert W. Pasco

IPC: H01J2964

CPC classification number: H01J29/467 ,  H01J31/127

Abstract: The present invention relates generally to a new electrode forming metal/magnetic-ceramic laminate with through-holes and process thereof. More particularly, the invention encompasses a new process for fabrication of a large area ceramic laminate magnet with a significant number of holes, integrated metal plate(s) and co-sintered electrodes for electron and electron beam control. The present invention also relates to a magnetic matrix display (MMD), and electron beam source, and methods of manufacture thereof.

Abstract translation: 本发明一般涉及具有通孔的新型电极形成金属/磁陶瓷层压体及其工艺。 更具体地，本发明包括用于制造具有大量孔的大面积陶瓷层压体磁体的新方法，用于电子和电子束控制的集成金属板和共烧结电极。 本发明还涉及磁矩阵显示器（MMD）和电子束源，及其制造方法。