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公开(公告)号：US09251094B2
公开(公告)日：2016-02-02
申请号：US14675325
申请日：2015-03-31
Applicant: Intel Corporation
Inventor： Steven M. Bennett , Andrew V. Anderson , Gilbert Neiger , Richard A Uhlig , Scott Dion Rodgers , Rajesh M. Sankaran , Camron Rust , Sebastian Schoenberg
CPC classification number: G06F12/1027 , G06F9/3004 , G06F9/30076 , G06F9/45558 , G06F12/0246 , G06F12/0875 , G06F12/1009 , G06F12/1036 , G06F12/1054 , G06F2009/45583 , G06F2212/152 , G06F2212/2022 , G06F2212/452 , G06F2212/50 , G06F2212/65 , G06F2212/657 , G06F2212/68 , G06F2212/683 , G06F2212/7201
Abstract: A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest physical address) to a physical address of the host of the virtualization based system (host physical address), and stored in a translation lookaside buffer (TLB), with a corresponding mapping stored in an extended paging table (EPT) of the virtualization based system.
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公开(公告)号：US20160019166A1
公开(公告)日：2016-01-21
申请号：US14867027
申请日：2015-09-28
Applicant: Intel Corporation
Inventor： Steven M. Bennett , Andrew V. Anderson , Gilbert Neiger , Richard Uhlig , Scott Dion Rodgers , Rajesh M. Sankaran , Camron Rust , Sebastian Schoenberg
CPC classification number: G06F12/1027 , G06F9/3004 , G06F9/30076 , G06F9/45558 , G06F12/0246 , G06F12/0875 , G06F12/1009 , G06F12/1036 , G06F12/1054 , G06F2009/45583 , G06F2212/152 , G06F2212/2022 , G06F2212/452 , G06F2212/50 , G06F2212/65 , G06F2212/657 , G06F2212/68 , G06F2212/683 , G06F2212/7201
Abstract: A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest physical address) to a physical address of the host of the virtualization based system (host physical address), and stored in a translation lookaside buffer (TLB), with a corresponding mapping stored in an extended paging table (EPT) of the virtualization based system.
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公开(公告)号：US20160019162A1
公开(公告)日：2016-01-21
申请号：US14867020
申请日：2015-09-28
Applicant: Intel Corporation
Inventor： Steven M. Bennett , Andrew V. Anderson , Gilbert Neiger , Richard A. Uhlig , Scott Dion Rodgers , Rajesh M. Sankaran , Camron Rust , Sebastian Schoenberg
CPC classification number: G06F12/1027 , G06F9/3004 , G06F9/30076 , G06F9/45558 , G06F12/0246 , G06F12/0875 , G06F12/1009 , G06F12/1036 , G06F12/1054 , G06F2009/45583 , G06F2212/152 , G06F2212/2022 , G06F2212/452 , G06F2212/50 , G06F2212/65 , G06F2212/657 , G06F2212/68 , G06F2212/683 , G06F2212/7201
Abstract: A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest physical address) to a physical address of the host of the virtualization based system (host physical address), and stored in a translation lookaside buffer (TLB), with a corresponding mapping stored in an extended paging table (EPT) of the virtualization based system.
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公开(公告)号：US20160019140A1
公开(公告)日：2016-01-21
申请号：US14867023
申请日：2015-09-28
Applicant: Intel Corporation
Inventor： Steven M. Bennett , Andrew V. Anderson , Gilbert Neiger , Richard A. Uhlig , Scott Dion Rodgers , Rajesh M. Sankaran , Camron Rust , Sebastian Schoenberg
CPC classification number: G06F12/1027 , G06F9/3004 , G06F9/30076 , G06F9/45558 , G06F12/0246 , G06F12/0875 , G06F12/1009 , G06F12/1036 , G06F12/1054 , G06F2009/45583 , G06F2212/152 , G06F2212/2022 , G06F2212/452 , G06F2212/50 , G06F2212/65 , G06F2212/657 , G06F2212/68 , G06F2212/683 , G06F2212/7201
Abstract: A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest physical address) to a physical address of the host of the virtualization based system (host physical address), and stored in a translation lookaside buffer (TLB), with a corresponding mapping stored in an extended paging table (EPT) of the virtualization based system.
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公开(公告)号：US20150205728A1
公开(公告)日：2015-07-23
申请号：US14675325
申请日：2015-03-31
Applicant: Intel Corporation
Inventor： Steven M. Bennett , Andrew V. Anderson , Gilbert Neiger , Richard Uhlig , Dion Rodgers , Rajesh M. Sankaran , Camron Rust , Sebastian Schoenberg
CPC classification number: G06F12/1027 , G06F9/3004 , G06F9/30076 , G06F9/45558 , G06F12/0246 , G06F12/0875 , G06F12/1009 , G06F12/1036 , G06F12/1054 , G06F2009/45583 , G06F2212/152 , G06F2212/2022 , G06F2212/452 , G06F2212/50 , G06F2212/65 , G06F2212/657 , G06F2212/68 , G06F2212/683 , G06F2212/7201
Abstract: A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest physical address) to a physical address of the host of the virtualization based system (host physical address), and stored in a translation lookaside buffer (TLB), with a corresponding mapping stored in an extended paging table (EPT) of the virtualization based system.
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Patent Agency Ranking
46.发明申请公开(公告)号：US20150205723A1
公开(公告)日：2015-07-23
申请号：US14675297
申请日：2015-03-31
Applicant: Intel Corporation
Inventor： Steven M. Bennett , Andrew V. Anderson , Gilbert Neiger , Richard Uhlig , Dion Rodgers , Rajesh M. Sankaran , Camron Rust , Sebastian Schoenberg
CPC classification number: G06F12/1027 , G06F9/3004 , G06F9/30076 , G06F9/45558 , G06F12/0246 , G06F12/0875 , G06F12/1009 , G06F12/1036 , G06F12/1054 , G06F2009/45583 , G06F2212/152 , G06F2212/2022 , G06F2212/452 , G06F2212/50 , G06F2212/65 , G06F2212/657 , G06F2212/68 , G06F2212/683 , G06F2212/7201
Abstract: A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest physical address) to a physical address of the host of the virtualization based system (host physical address), and stored in a translation lookaside buffer (TLB), with a corresponding mapping stored in an extended paging table (EPT) of the virtualization based system.
Abstract translation: 一种处理器，包括执行指令以使来自基于虚拟化的系统的客户机的物理地址（客户物理地址）到基于虚拟化系统的主机的物理地址（主机物理地址）的映射同步的指令，并且存储在 翻译后备缓冲器（TLB），其中相应的映射存储在基于虚拟化的系统的扩展分页表（EPT）中。
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公开(公告)号：US12197601B2
公开(公告)日：2025-01-14
申请号：US17560193
申请日：2021-12-22
Applicant: Intel Corporation
Inventor： Ren Wang , Sameh Gobriel , Somnath Paul , Yipeng Wang , Priya Autee , Abhirupa Layek , Shaman Narayana , Edwin Verplanke , Mrittika Ganguli , Jr-Shian Tsai , Anton Sorokin , Suvadeep Banerjee , Abhijit Davare , Desmond Kirkpatrick , Rajesh M. Sankaran , Jaykant B. Timbadiya , Sriram Kabisthalam Muthukumar , Narayan Ranganathan , Nalini Murari , Brinda Ganesh , Nilesh Jain
Abstract: Examples described herein relate to offload circuitry comprising one or more compute engines that are configurable to perform a workload offloaded from a process executed by a processor based on a descriptor particular to the workload. In some examples, the offload circuitry is configurable to perform the workload, among multiple different workloads. In some examples, the multiple different workloads include one or more of: data transformation (DT) for data format conversion, Locality Sensitive Hashing (LSH) for neural network (NN), similarity search, sparse general matrix-matrix multiplication (SpGEMM) acceleration of hash based sparse matrix multiplication, data encode, data decode, or embedding lookup.
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公开(公告)号：US12135981B2
公开(公告)日：2024-11-05
申请号：US18207870
申请日：2023-06-09
Applicant: Intel Corporation
Inventor： Rajesh M. Sankaran , Gilbert Neiger , Narayan Ranganathan , Stephen R. Van Doren , Joseph Nuzman , Niall D. McDonnell , Michael A. O'Hanlon , Lokpraveen B. Mosur , Tracy Garrett Drysdale , Eriko Nurvitadhi , Asit K. Mishra , Ganesh Venkatesh , Deborah T. Marr , Nicholas P. Carter , Jonathan D. Pearce , Edward T. Grochowski , Richard J. Greco , Robert Valentine , Jesus Corbal , Thomas D. Fletcher , Dennis R. Bradford , Dwight P. Manley , Mark J. Charney , Jeffrey J. Cook , Paul Caprioli , Koichi Yamada , Kent D. Glossop , David B. Sheffield
Abstract: Embodiments of systems, methods, and apparatuses for heterogeneous computing are described. In some embodiments, a hardware heterogeneous scheduler dispatches instructions for execution on one or more plurality of heterogeneous processing elements, the instructions corresponding to a code fragment to be processed by the one or more of the plurality of heterogeneous processing elements, wherein the instructions are native instructions to at least one of the one or more of the plurality of heterogeneous processing elements.
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49.发明授权公开(公告)号：US12117910B2
公开(公告)日：2024-10-15
申请号：US17868596
申请日：2022-07-19
Applicant: Intel Corporation
Inventor： Nrupal Jani , Manasi Deval , Anjali Singhai Jain , Parthasarathy Sarangam , Mitu Aggarwal , Neerav Parikh , Alexander H. Duyck , Kiran Patil , Rajesh M. Sankaran , Sanjay K. Kumar , Utkarsh Y. Kakaiya , Philip Lantz , Kun Tian
CPC classification number: G06F11/2023 , G06F3/0622 , G06F3/0631 , G06F3/0659 , G06F3/0673 , G06F9/45558 , G06F9/4856 , G06F11/2007 , G06F13/1668 , G06F13/4068 , G06F13/4221 , G06F13/4282 , G06F15/17331 , G06F2009/45562 , G06F2009/4557 , G06F2009/45579 , G06F2009/45583 , G06F2009/45595 , G06F2201/805 , G06F2201/815 , G06F2213/0026
Abstract: Examples may include a method of instantiating a virtual machine, instantiating a virtual device to transmit data to and receive data from assigned resources of a shared physical device; and assigning the virtual device to the virtual machine, the virtual machine to transmit data to and receive data from the physical device via the virtual device.
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公开(公告)号：US12020031B2
公开(公告)日：2024-06-25
申请号：US17334901
申请日：2021-05-31
Applicant: Intel Corporation
Inventor： Michael Mishaeli , Jason W. Brandt , Gilbert Neiger , Asit K. Mallick , Rajesh M. Sankaran , Raghunandan Makaram , Benjamin C. Chaffin , James B. Crossland , H. Peter Anvin
CPC classification number: G06F9/3009 , G06F9/3004 , G06F9/30076 , G06F9/3851 , G06F9/485 , G06F13/4068
Abstract: A processor of an aspect includes a decode unit to decode a user-level suspend thread instruction that is to indicate a first alternate state. The processor also includes an execution unit coupled with the decode unit. The execution unit is to perform the instruction at a user privilege level. The execution unit in response to the instruction, is to: (a) suspend execution of a user-level thread, from which the instruction is to have been received; (b) transition a logical processor, on which the user-level thread was to have been running, to the indicated first alternate state; and (c) resume the execution of the user-level thread, when the logical processor is in the indicated first alternate state, with a latency that is to be less than half a latency that execution of a thread can be resumed when the logical processor is in a halt processor power state.
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