公开(公告)号：US12153222B2

公开(公告)日：2024-11-26

申请号：US18360193

申请日：2023-07-27

Applicant: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.

Inventor： Rajesh Katkar ,  Belgacem Haba

IPC: G02B27/01 ,  G02B27/10 ,  G02B27/14 ,  H01L25/075

Abstract: A bonded optical device is disclosed. The bonded optical device can include a first optical element, a second optical element, and an optical pathway. The first optical element has a first array of optical emitters configured to emit light of a first color. The first optical element is bonded to at least one processor element, the at least one processor element including active circuitry configured to control operation of the first optical element. The second optical element has a second array of optical emitters configured to emit light of a second color different from the first color. The second optical element is bonded to the at least one processor element. The optical pathway is optically coupled with the first and second optical elements. The optical pathway is configured to transmit a superposition of light from the first and second optical emitters to an optical output to be viewed by users.

公开(公告)号：US20240387439A1

公开(公告)日：2024-11-21

申请号：US18784724

申请日：2024-07-25

Applicant: Adeia Semiconductor Bonding Technologies Inc.

Inventor： Belgacem Haba ,  Laura Wills Mirkarimi ,  Javier A. DeLaCruz ,  Rajesh Katkar ,  Cyprian Emeka Uzoh ,  Guilian Gao ,  Thomas Workman

IPC: H01L23/00 ,  H01L23/31

Abstract: A bonded structure can comprise a first element and a second element. The first element has a first dielectric layer including a first bonding surface and at least one first side surface of the first element. The second element has a second dielectric layer including a second bonding surface and at least one second side surface of the second element. The second bonding surface of the second element is directly bonded to the first bonding surface of the first element without an adhesive.

公开(公告)号：US20240387323A1

公开(公告)日：2024-11-21

申请号：US18512547

申请日：2023-11-17

Applicant: Adeia Semiconductor Bonding Technologies Inc.

Inventor： Belgacem Haba ,  Rajesh Katkar

IPC: H01L23/473 ,  H01L23/00 ,  H01L23/427 ,  H01L23/498 ,  H01L25/18 ,  H10B80/00

Abstract: The present disclosure provides for integrated cooling systems including an integrated cooling assembly. The integrated cooling assembly includes a semiconductor device having an active side and a backside opposite the active side. The integrated cooling assembly includes a plurality of stacked and bonded layers that collectively form a cold plate, the cold plate comprising (i) a first side and a second side opposite the first side, the first side having a base surface, a support feature that extends downwardly from the base surface, and sidewalls that extend downwardly from the base surface and surround base surface and the support feature, and (ii) a first interconnect vertically disposed through the support feature, where the first interconnect is electrically coupled to the semiconductor device through direct hybrid bonds formed between the cold plate and the semiconductor device.

公开(公告)号：US20240312951A1

公开(公告)日：2024-09-19

申请号：US18183768

申请日：2023-03-14

Applicant: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.

Inventor： Cyprian Emeka Uzoh ,  Jeremy Alfred Theil ,  Gaius Gillman Fountain, JR. ,  Belgacem Haba ,  Rajesh Katkar

IPC: H01L23/00 ,  H01L21/027 ,  H01L21/56 ,  H01L23/12 ,  H01L25/16

CPC classification number: H01L24/80 ,  H01L21/0273 ,  H01L21/561 ,  H01L23/12 ,  H01L24/03 ,  H01L24/08 ,  H01L24/96 ,  H01L25/162 ,  H01L25/167 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03831 ,  H01L2224/03845 ,  H01L2224/08145 ,  H01L2224/80011 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/80948 ,  H01L2224/96 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/12043

Abstract: An element includes a substrate and a surface layer on the substrate. The surface layer includes at least one first region comprising an optically transparent and electrically insulative first material and at least one second region at least partially embedded in the at least one first region. The at least one second region comprises an optically transparent and electrically conductive second material.

公开(公告)号：US20240234353A1

公开(公告)日：2024-07-11

申请号：US18451388

申请日：2023-08-17

Applicant: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.

Inventor： Belgacem Haba

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/538 ,  H01L25/065

CPC classification number: H01L24/08 ,  H01L23/3121 ,  H01L23/5383 ,  H01L24/05 ,  H01L24/80 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0655 ,  H01L2224/05647 ,  H01L2224/08235

Abstract: A bonded structure is disclosed. The bonded structure can include an interconnect structure. The bonded structure can also include a first die directly bonded to the interconnect structure. The bonded structure can also include a second die mounted to the interconnect structure. The second die is spaced apart from the first die laterally along an upper surface of the interconnect structure. The second die is electrically connected with the first die at least partially through the interconnect structure. The bonded structure can further include a dielectric layer that is disposed over the upper surface of the interconnect structure between the first die and the second die.

公开(公告)号：US20240203948A1

公开(公告)日：2024-06-20

申请号：US18589231

申请日：2024-02-27

Applicant: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.

Inventor： Cyprian Emeka Uzoh ,  Rajesh Katkar ,  Thomas Workman ,  Guilian Gao ,  Gaius Gillman Fountain, JR. ,  Laura Wills Mirkarimi ,  Belgacem Haba ,  Gabriel Z. Guevara ,  Joy Watanabe

IPC: H01L25/065 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L25/0657 ,  H01L21/561 ,  H01L23/3121 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2924/3511 ,  H01L2924/35121

Abstract: Direct bonded stack structures for increased reliability and improved yields in microelectronics are provided. Structural features and stack configurations are provided for memory modules and 3DICs to reduce defects in vertically stacked dies. Example processes alleviate warpage stresses between a thicker top die and direct bonded dies beneath it, for example. An etched surface on the top die may relieve warpage stresses. An example stack may include a compliant layer between dies. Another stack configuration replaces the top die with a layer of molding material to circumvent warpage stresses. An array of cavities on a bonding surface can alleviate stress forces. One or more stress balancing layers may also be created on a side of the top die or between other dies to alleviate or counter warpage. Rounding of edges can prevent stresses and pressure forces from being destructively transmitted through die and substrate layers. These measures may be applied together or in combinations in a single package.

公开(公告)号：US20240128186A1

公开(公告)日：2024-04-18

申请号：US18394558

申请日：2023-12-22

Applicant: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.

Inventor： Belgacem Haba ,  Javier A. DeLaCruz

IPC: H01L23/522 ,  H01L23/00 ,  H01L23/528 ,  H01L23/538 ,  H01L25/16

CPC classification number: H01L23/5223 ,  H01L23/5226 ,  H01L23/5286 ,  H01L23/5383 ,  H01L23/5389 ,  H01L24/17 ,  H01L25/16 ,  H01L28/60 ,  H01L2924/1205

Abstract: In various embodiments, a passive electronic component is disclosed. The passive electronic component can have a first surface and a second surface opposite the first surface. The passive electronic component can include a nonconductive material and a capacitor embedded within the nonconductive material. The capacitor can have a first electrode, a second electrode, and a dielectric material disposed between the first and second electrodes. The first electrode can comprise a first conductive layer and a plurality of conductive fibers extending from and electrically connected to the first conductive layer. A first conductive via can extend through the passive electronic component from the first surface to the second surface, with the first conductive via electrically connected to the first electrode.

公开(公告)号：US20240096823A1

公开(公告)日：2024-03-21

申请号：US18520337

申请日：2023-11-27

Applicant: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.

Inventor： Javier A. DeLaCruz ,  Belgacem Haba ,  Rajesh Katkar

IPC: H01L23/00 ,  H01L21/66 ,  H01L23/528

CPC classification number: H01L23/573 ,  H01L22/34 ,  H01L23/528 ,  H01L23/562 ,  H01L24/05 ,  H01L24/08 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L24/49 ,  H01L2224/08237 ,  H01L2224/29082 ,  H01L2224/29187 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48225 ,  H01L2224/49171 ,  H01L2224/73215

Abstract: A bonded structure is disclosed. The bonded structure can include a semiconductor element comprising active circuitry. The bonded structure can include a protective element directly bonded to the semiconductor element without an adhesive along a bonding interface. The protective element can include an obstructive material disposed over at least a portion of the active circuitry. The obstructive material can be configured to obstruct external access to the active circuitry. The bonded structure can include a disruption structure configured to disrupt functionality of the at least a portion of the active circuitry upon debonding of the protective element from the semiconductor element.

公开(公告)号：US20230420399A1

公开(公告)日：2023-12-28

申请号：US18462691

申请日：2023-09-07

Applicant: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.

Inventor： Belgacem Haba ,  Rajesh Katkar ,  Ilyas Mohammed ,  Javier A. DeLaCruz

IPC: H01L23/00 ,  H01L21/78

CPC classification number: H01L24/08 ,  H01L24/80 ,  H01L24/94 ,  H01L21/78 ,  H01L2224/80896 ,  H01L2224/08146 ,  H01L2224/80006 ,  H01L2224/80895

Abstract: A bonded structure can include a first reconstituted element comprising a first element and having a first side comprising a first bonding surface and a second side opposite the first side. The first reconstituted element can comprise a first protective material disposed about a first sidewall surface of the first element. The bonded structure can comprise a second reconstituted element comprising a second element and having a first side comprising a second bonding surface and a second side opposite the first side. The first reconstituted element can comprise a second protective material disposed about a second sidewall surface of the second element. The second bonding surface of the first side of the second reconstituted element can be directly bonded to the first bonding surface of the first side of the first reconstituted element without an intervening adhesive along a bonding interface.

公开(公告)号：US11848284B2

公开(公告)日：2023-12-19

申请号：US17834737

申请日：2022-06-07

Applicant: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.

Inventor： Javier A DeLaCruz ,  Belgacem Haba ,  Rajesh Katkar

IPC: H01L23/00 ,  H01L21/66 ,  H01L23/528

CPC classification number: H01L23/573 ,  H01L22/34 ,  H01L23/528 ,  H01L23/562 ,  H01L24/05 ,  H01L24/08 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L24/49 ,  H01L2224/08237 ,  H01L2224/29082 ,  H01L2224/29187 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48225 ,  H01L2224/49171 ,  H01L2224/73215

Abstract: A bonded structure is disclosed. The bonded structure can include a semiconductor element comprising active circuitry. The bonded structure can include a protective element directly bonded to the semiconductor element without an adhesive along a bonding interface. The protective element can include an obstructive material disposed over at least a portion of the active circuitry. The obstructive material can be configured to obstruct external access to the active circuitry. The bonded structure can include a disruption structure configured to disrupt functionality of the at least a portion of the active circuitry upon debonding of the protective element from the semiconductor element.