公开(公告)号：US20120241972A1

公开(公告)日：2012-09-27

申请号：US13070772

申请日：2011-03-24

申请人： Yu-Ren CHEN ,  Kuo-Ji CHEN ,  Guang-Cheng WANG

发明人： Yu-Ren CHEN ,  Kuo-Ji CHEN ,  Guang-Cheng WANG

IPC分类号： H01L23/50 ,  H01L21/441

CPC分类号： H01L23/5286 ,  H01L23/60 ,  H01L24/03 ,  H01L24/05 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0557 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2924/00014 ,  H01L2224/05552

摘要： An integrated circuit layout for an Input Output (IO) cell includes at least three metal layers. An IO pad is disposed directly over a top metal layer of the at least three metal layers. At least top two metal layers of the at least three metal layers provide a power bus and a ground bus.

摘要翻译： 用于输入输出（IO）单元的集成电路布局包括至少三个金属层。 IO垫直接设置在至少三个金属层的顶部金属层上。 至少三个金属层的至少顶部两个金属层提供电力总线和接地总线。

公开(公告)号：US20110183466A1

公开(公告)日：2011-07-28

申请号：US13082096

申请日：2011-04-07

申请人： Yu-Ren CHEN ,  Geng-Shin Shen ,  Tz-Cheng Chiu

发明人： Yu-Ren CHEN ,  Geng-Shin Shen ,  Tz-Cheng Chiu

IPC分类号： H01L21/56

CPC分类号： H01L21/561 ,  H01L21/568 ,  H01L23/3107 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/20 ,  H01L2224/92 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/10158 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/3511 ,  H01L2224/96 ,  H01L2224/82 ,  H01L2924/00

摘要： A packaging method is disclosed that comprises attaching a plurality of dice, each having a plurality of bonding pads disposed on an active surface, to an adhesive layer on a substrate. A polymer material is formed over at least a portion of both the substrate and the plurality of dice and a molding apparatus is used on the substrate to force the polymer material to substantially fill around the plurality of dice. The molding apparatus is removed to expose a surface of the polymer material and a plurality of cutting streets is formed on an exposed surface of the polymer material. The substrate is removed to expose the active surface of the plurality of dice.

摘要翻译： 公开了一种包装方法，其包括将多个具有设置在活性表面上的多个接合焊盘附着到基板上的粘合剂层的芯片。 聚合物材料形成在基底和多个骰子的至少一部分上，并且在基底上使用模塑设备以迫使聚合物材料基本上填充在多个骰子周围。 去除模制设备以暴露聚合物材料的表面，并且在聚合物材料的暴露表面上形成多个切割街道。 去除衬底以暴露多个裸片的活性表面。

公开(公告)号：US20110163426A1

公开(公告)日：2011-07-07

申请号：US13048259

申请日：2011-03-15

申请人： GENG-SHIN SHEN ,  Yu-Ren Chen

发明人： GENG-SHIN SHEN ,  Yu-Ren Chen

IPC分类号： H01L23/495

CPC分类号： H01L25/50 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/25 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0655 ,  H01L33/486 ,  H01L33/54 ,  H01L2221/68359 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/20 ,  H01L2224/211 ,  H01L2224/24137 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/0102 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/01094 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/15311 ,  H01L2924/3511 ,  H01L2933/005 ,  H01L2933/0066 ,  H01L2224/82 ,  H01L2924/00

摘要： A dice rearrangement package structure is provided, which a dice having an active surface and a bottom surface, and a plurality of pads is disposed on the active surface; a package body is provided to cover the dices and the plurality of pads being exposed; one ends of plurality of metal traces is electrically connected to the each pads; a protection layer is provided to cover the active surface and the other ends of the exposed metal traces is electrically connected to the plurality of conductive elements, the characteristic in that the package body is a B-stage material.

摘要翻译： 提供了具有活性表面和底表面的骰子，并且多个衬垫设置在活性表面上的骰子重排包装结构， 提供包装体以覆盖所述骰子并且所述多个垫被暴露; 多个金属迹线的一端电连接到每个焊盘; 提供保护层以覆盖有源表面，并且暴露的金属迹线的另一端电连接到多个导电元件，其特征在于封装体是B级材料。

公开(公告)号：US07927922B2

公开(公告)日：2011-04-19

申请号：US12191382

申请日：2008-08-14

申请人： Geng-Shin Shen ,  Yu-Ren Chen

发明人： Geng-Shin Shen ,  Yu-Ren Chen

IPC分类号： H01L21/44 ,  H01L21/48 ,  H01L21/50

CPC分类号： H01L25/50 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/25 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0655 ,  H01L33/486 ,  H01L33/54 ,  H01L2221/68359 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/20 ,  H01L2224/211 ,  H01L2224/24137 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/0102 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/01094 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/15311 ,  H01L2924/3511 ,  H01L2933/005 ,  H01L2933/0066 ,  H01L2224/82 ,  H01L2924/00

摘要： A dice rearrangement package structure is provided, which a dice having an active surface and a bottom surface, and a plurality of pads is disposed on the active surface; a package body is provided to cover the dices and the plurality of pads being exposed; one ends of plurality of metal traces is electrically connected to the each pads; a protection layer is provided to cover the active surface and the other ends of the exposed metal traces is electrically connected to the plurality of conductive elements, the characteristic in that the package body is a B-stage material.

摘要翻译： 提供了具有活性表面和底表面的骰子，并且多个衬垫设置在活性表面上的骰子重排包装结构， 提供包装体以覆盖所述骰子并且所述多个垫被暴露; 多个金属迹线的一端电连接到每个焊盘; 提供保护层以覆盖有源表面，并且暴露的金属迹线的另一端电连接到多个导电元件，其特征在于封装体是B级材料。

公开(公告)号：US07781878B2

公开(公告)日：2010-08-24

申请号：US12017014

申请日：2008-01-19

申请人： Yu-Ren Chen ,  Yeong-Jyh Lin

发明人： Yu-Ren Chen ,  Yeong-Jyh Lin

IPC分类号： H01L23/02 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L23/49575 ,  H01L23/525 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48147 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/83191 ,  H01L2225/06562 ,  H01L2924/01005 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A die-stacked package structure, wherein a plurality of dies are stacked on the substrate with a rotation so that a plurality of metallic ends and the metal pad on each die on the substrate can all be exposed; a plurality of metal wires are provided for electrically connecting the plurality of metal pads on the plurality of dies with the plurality metallic ends on the substrate in one wire bonding process; then an encapsulate is provided for covering the plurality of stacked dies, a plurality of metal wires and the plurality of metallic ends on the substrate.

摘要翻译： 一种管芯堆叠封装结构，其中多个管芯以旋转方式堆叠在所述衬底上，使得能够暴露所述衬底上的每个管芯上的多个金属端和所述金属焊盘; 提供多个金属线，用于在一个引线接合过程中将多个金属焊盘上的多个金属焊盘与多个金属端部电连接在基板上; 然后提供封装以覆盖多个堆叠的裸片，多个金属线以及衬底上的多个金属端。

公开(公告)号：US20070170961A1

公开(公告)日：2007-07-26

申请号：US11366694

申请日：2006-03-02

申请人： Chun-Yao Liao ,  Yu-Ren Chen

发明人： Chun-Yao Liao ,  Yu-Ren Chen

IPC分类号： H03L7/00

CPC分类号： H03K17/223 ,  G06F1/24 ,  H03K17/161 ,  H03K17/284

摘要： Disclosed is an improved circuit and method for generating a power on reset signal, the circuit being a two-stage circuit comprising a delay-stage circuit and an output-stage circuit. The delay-stage circuit delays a time for a power on reset signal generated in the output-stage circuit changing from low to high, so that a power voltage having a low rising speed may be normally reset. Further, the two stages provide charging paths and discharging paths so that the power on reset signal may be prevented from changing from high to low when it has changed from low to high, when noises are presented on the power voltage.

摘要翻译： 公开了一种用于产生上电复位信号的改进的电路和方法，该电路是包括延迟级电路和输出级电路的两级电路。 延迟级电路延迟在输出级电路中产生的上电复位信号从低变为高的时间，使得具有低上升速度的电源电压可以被正常复位。 此外，两级提供充电路径和放电路径，使得当在电源电压上呈现噪声时，当从低电平变为高电平时，可以防止上电复位信号从高电平变为低电平。