公开(公告)号：US20080220574A1

公开(公告)日：2008-09-11

申请号：US11681987

申请日：2007-03-05

Applicant: Li-Shian Jeng ,  Cheng-Tung Huang ,  Shyh-Fann Ting ,  Wen-Han Hung ,  Kun-Hsien Lee ,  Meng-Yi Wu ,  Tzyy-Ming Cheng

Inventor： Li-Shian Jeng ,  Cheng-Tung Huang ,  Shyh-Fann Ting ,  Wen-Han Hung ,  Kun-Hsien Lee ,  Meng-Yi Wu ,  Tzyy-Ming Cheng

IPC: H01L21/8238 ,  H01L21/336

CPC classification number: H01L21/823807 ,  H01L21/26506 ,  H01L21/823814 ,  H01L29/1083 ,  H01L29/165 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7847 ,  H01L29/7848

Abstract: A method of fabricating a complementary metal oxide semiconductor (CMOS) device is provided. A first conductive type MOS transistor including a source/drain region using a semiconductor compound as major material is formed in a first region of a substrate. A second conductive type MOS transistor is formed in a second region of the substrate. Next, a pre-amorphous implantation (PAI) process is performed to amorphize a gate conductive layer of the second conductive type MOS transistor. Thereafter, a stress-transfer-scheme (STS) is formed on the substrate in the second region to generate a stress in the gate conductive layer. Afterwards, a rapid thermal annealing (RTA) process is performed to activate the dopants in the source/drain region. Then, the STS is removed.

Abstract translation: 提供了制造互补金属氧化物半导体（CMOS）器件的方法。 在衬底的第一区域中形成包括使用半导体化合物作为主要材料的源/漏区的第一导电型MOS晶体管。 在基板的第二区域中形成第二导电型MOS晶体管。 接下来，执行预非晶体注入（PAI）工艺以使第二导电型MOS晶体管的栅极导电层非晶化。 此后，在第二区域中的基板上形成应力转移方案（STS），以在栅极导电层中产生应力。 之后，进行快速热退火（RTA）处理以激活源极/漏极区域中的掺杂剂。 然后，STS被删除。

公开(公告)号：US20080042210A1

公开(公告)日：2008-02-21

申请号：US11465455

申请日：2006-08-18

Applicant: Wen-Han Hung ,  Cheng-Tung Huang ,  Li-Shian Jeng ,  Kun-Hsien Lee ,  Shyh-Fann Ting ,  Tzyy-Ming Cheng ,  Chia-Wen Liang

Inventor： Wen-Han Hung ,  Cheng-Tung Huang ,  Li-Shian Jeng ,  Kun-Hsien Lee ,  Shyh-Fann Ting ,  Tzyy-Ming Cheng ,  Chia-Wen Liang

IPC: H01L29/78 ,  H01L21/8238

CPC classification number: H01L21/823807 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/7843

Abstract: A method of fabricating a semiconductor device is provided. A substrate is first provided, and than several IO devices and several core devices are formed on the substrate, wherein those IO devises include IO PMOS and IO NMOS, and those core devises include core PMOS and core NMOS. Thereafter, a buffer layer is formed on the substrate, and then the buffer layer except a surface of the IO PMOS is removed in order to reduce the negative bias temperature instability (NBTI) of the IO PMOS. Afterwards, a tensile contact etching stop layer (CESL) is formed on the IO NMOS and the core NMOS, and a compressive CESL is formed the core PMOS.

Abstract translation: 提供一种制造半导体器件的方法。 首先提供衬底，并且在衬底上形成多个IO器件和多个核心器件，其中这些IO器件包括IO PMOS和IO NMOS，并且那些芯部器件包括核心PMOS和核心NMOS。 此后，在衬底上形成缓冲层，然后除去IO PMOS的表面以外的缓冲层，以便减少IO PMOS的负偏压温度不稳定性（NBTI）。 之后，在IO NMOS和核心NMOS上形成一个拉伸接触蚀刻停止层（CESL），并且形成一个压电CESL的芯体PMOS。

公开(公告)号：US07250332B2

公开(公告)日：2007-07-31

申请号：US10711038

申请日：2004-08-19

Applicant: Wen-Koi Lai ,  Tung-Hsing Lee ,  Tai-Yuan Lee ,  Yu-Lung Chin ,  Yi-Chia Lee ,  Shyh-Fann Ting

Inventor： Wen-Koi Lai ,  Tung-Hsing Lee ,  Tai-Yuan Lee ,  Yu-Lung Chin ,  Yi-Chia Lee ,  Shyh-Fann Ting

IPC: H01L21/8238

CPC classification number: H01L21/823864 ,  H01L21/26586 ,  H01L21/823814 ,  H01L21/84 ,  H01L29/6659

Abstract: The present invention discloses a method for fabricating a semiconductor device. A substrate is provided. At least one first and second gate structure, having sidewalls, are included on a surface of the substrate. A first ion implantation process is performed to form a shallow-junction doping region of a first conductive type in the substrate next to each of the sidewalls of the first gate structure, followed by the formation of offset spacers on each of the sidewalls of the first and second gate structure. A second ion implantation process is performed to form a shallow-junction doping region of a second conductive type in the substrate next to the offset spacer on each of the sidewalls of the second gate structure.

Abstract translation: 本发明公开了一种半导体器件的制造方法。 提供基板。 具有侧壁的至少一个第一和第二栅极结构被包括在基板的表面上。 执行第一离子注入工艺以在基板中的第一栅极结构的每个侧壁旁边形成第一导电类型的浅结掺杂区域，随后在第一栅极结构的每个侧壁上形成偏置间隔物 和第二门结构。 执行第二离子注入工艺以在第二栅极结构的每个侧壁上的偏移间隔物旁边的衬底中形成第二导电类型的浅结掺杂区域。

公开(公告)号：US06877385B2

公开(公告)日：2005-04-12

申请号：US10085256

申请日：2001-10-22

Applicant: Yean-Kuen Fang ,  Ming-Shanng Ju ,  Jyh-Jier Ho ,  Gin-Shin Chen ,  Ming-Chun Hsieh ,  Shyh-Fann Ting ,  Chung-Hsien Yang

Inventor： Yean-Kuen Fang ,  Ming-Shanng Ju ,  Jyh-Jier Ho ,  Gin-Shin Chen ,  Ming-Chun Hsieh ,  Shyh-Fann Ting ,  Chung-Hsien Yang

IPC: A61B5/103 ,  B81B3/00 ,  G01L1/18 ,  G01B7/16

CPC classification number: A61B5/103 ,  A61B2562/028 ,  A61B2562/12 ,  G01L1/18

Abstract: There is disclosed a semiconductor sensor for measuring the contact shear stress distribution between the socket of an above-knee (AK) prostheses and the soft tissue of an amputee's stump. The sensor is fabricated by the micro-electro-mechanical system (MEMS) technology, and its main sensing part is 2-X shaped with a flange structure. The sensor is prepared by anisotropic wet etching of bulk silicon in KOH solution and a square flange above the sensing diaphragm is formed through surface micromachining of deposited SiO2 thin film. This invention has the following characteristics: piezo-resistivity of the monolithic silicon will be utilized to convert shear deformation of the sensor into an electrical signal and a micro sensor which can measure the shear force vector acting on the sensing flange.

Abstract translation: 公开了一种半导体传感器，用于测量膝盖（AK）假体的插座与截肢者残肢的软组织之间的接触剪切应力分布。 传感器采用微机电系统（MEMS）技术制造，其主感测部件采用2-X形法兰结构。 传感器通过在KOH溶液中的体硅的各向异性湿法蚀刻制备，并且通过沉积的SiO 2薄膜的表面微加工形成感测膜上方的方形凸缘。 本发明具有以下特征：单片硅的压阻电阻将用于将传感器的剪切变形转换为电信号，并且可以测量作用在感测凸缘上的剪切力矢量的微传感器。

公开(公告)号：US20140061842A1

公开(公告)日：2014-03-06

申请号：US13604380

申请日：2012-09-05

Applicant: Shyh-Fann Ting ,  Jiech-Fun Lu ,  Ming-I Wang ,  Yeur-Luen Tu ,  Ching-Chun Wang

Inventor： Shyh-Fann Ting ,  Jiech-Fun Lu ,  Ming-I Wang ,  Yeur-Luen Tu ,  Ching-Chun Wang

IPC: H01L27/146 ,  H01L31/18

CPC classification number: H01L27/1464 ,  H01L21/76838 ,  H01L27/14623 ,  H01L27/14687

Abstract: A method includes forming an opening extending from a back surface of a semiconductor substrate to a metal pad on a front side of the semiconductor substrate, and forming a first conductive layer including a first portion overlapping active image sensors in the semiconductor substrate, a second portion overlapping black reference image sensors in the semiconductor substrate, and a third portion in the opening to contact the metal pad. A second conductive layer is formed over and contacting the first conductive layer. A first patterning step is performed to remove the first and the second portions of the second conductive layer, wherein the first conductive layer is used as an etch stop layer. A second patterning step is performed to remove a portion of the first portion of the first conductive layer. The second and the third portions of the first conductive layer remain after the second patterning step.

Abstract translation: 一种方法包括形成从半导体衬底的背表面延伸到半导体衬底的前侧上的金属焊盘的开口，以及在半导体衬底中形成包括与有源图像传感器重叠的第一部分的第一导电层，第二部分 半导体衬底中重叠的黑色参考图像传感器，以及开口中的与金属垫接触的第三部分。 在第一导电层上形成第二导电层并与第一导电层接触。 执行第一图案化步骤以去除第二导电层的第一和第二部分，其中第一导电层用作蚀刻停止层。 执行第二图案化步骤以去除第一导电层的第一部分的一部分。 在第二图案化步骤之后，第一导电层的第二和第三部分保留。

公开(公告)号：US08664073B2

公开(公告)日：2014-03-04

申请号：US12983894

申请日：2011-01-04

Applicant: Kun-Hsien Lee ,  Cheng-Tung Huang ,  Wen-Han Hung ,  Shyh-Fann Ting ,  Li-Shian Jeng ,  Meng-Yi Wu ,  Tzyy-Ming Cheng

Inventor： Kun-Hsien Lee ,  Cheng-Tung Huang ,  Wen-Han Hung ,  Shyh-Fann Ting ,  Li-Shian Jeng ,  Meng-Yi Wu ,  Tzyy-Ming Cheng

IPC: H01L21/8238

CPC classification number: H01L21/26506 ,  H01L21/26513 ,  H01L21/2658 ,  H01L21/26586 ,  H01L29/1083 ,  H01L29/6659 ,  H01L29/7833

Abstract: A method for fabricating complimentary metal-oxide-semiconductor field-effect transistor is disclosed. The method includes the steps of: (A) forming a first gate structure and a second gate structure on a substrate; (B) performing a first co-implantation process to define a first type source/drain extension region depth profile in the substrate adjacent to two sides of the first gate structure; (C) forming a first source/drain extension region in the substrate adjacent to the first gate structure; (D) performing a second co-implantation process to define a first pocket region depth profile in the substrate adjacent to two sides of the second gate structure; (E) performing a first pocket implantation process to form a first pocket region adjacent to two sides of the second gate structure.

Abstract translation: 公开了一种用于制造互补金属氧化物半导体场效应晶体管的方法。 该方法包括以下步骤：（A）在衬底上形成第一栅极结构和第二栅极结构; （B）执行第一共注入工艺以限定与所述第一栅极结构的两侧相邻的所述衬底中的第一类型源极/漏极延伸区域深度分布; （C）在与第一栅极结构相邻的衬底中形成第一源极/漏极延伸区域; （D）执行第二共注入工艺以限定与所述第二栅极结构的两侧相邻的所述衬底中的第一袋区深度分布; （E）执行第一口袋注入工艺以形成与第二栅极结构的两侧相邻的第一袋区域。

公开(公告)号：US20130285130A1

公开(公告)日：2013-10-31

申请号：US13743979

申请日：2013-01-17

Applicant: Shyh-Fann TING ,  Chih-Yu LAI ,  Cheng-Ta WU ,  Yeur-Luen TU ,  Ching-Chun WANG

Inventor： Shyh-Fann TING ,  Chih-Yu LAI ,  Cheng-Ta WU ,  Yeur-Luen TU ,  Ching-Chun WANG

IPC: H01L27/146

CPC classification number: H01L27/146 ,  H01L27/1463 ,  H01L27/1464 ,  H01L27/14683

Abstract: A semiconductor image sensor device having a negatively-charged layer includes a semiconductor substrate having a p-type region, a plurality of radiation-sensing regions in the p-type region proximate a front side of the semiconductor substrate, and a negatively-charged layer adjoining the p-type region proximate the plurality of radiation-sensing regions. The negatively-charged layer may be an oxygen-rich silicon oxide, a high-k metal oxide, or a silicon nitride formed as a liner in a shallow trench isolation feature, a sidewall spacer or an offset spacer of a transistor gate, a salicide-block layer, a buffer layer under a salicide-block layer, a backside surface layer, or a combination of these.

Abstract translation: 具有带负电荷层的半导体图像传感器装置包括具有p型区域的半导体衬底，在靠近半导体衬底的前侧的p型区域中的多个辐射感测区域和带负电荷层 邻近多个辐射感测区域的p型区域。 带负电荷的层可以是在浅沟槽隔离特征，侧壁间隔物或晶体管栅极的偏移间隔物中形成的富氧氧化硅，高k金属氧化物或形成为衬垫的氮化硅，自对准硅 - 嵌段层，在自对流硅化物阻挡层下面的缓冲层，背面表面层或它们的组合。

公开(公告)号：US08390073B2

公开(公告)日：2013-03-05

申请号：US13450444

申请日：2012-04-18

Applicant: Wen-Han Hung ,  Tsai-Fu Chen ,  Shyh-Fann Ting ,  Cheng-Tung Huang ,  Kun-Hsien Lee ,  Ta-Kang Lo ,  Tzyy-Ming Cheng

Inventor： Wen-Han Hung ,  Tsai-Fu Chen ,  Shyh-Fann Ting ,  Cheng-Tung Huang ,  Kun-Hsien Lee ,  Ta-Kang Lo ,  Tzyy-Ming Cheng

IPC: H01L29/76 ,  H01L29/94

CPC classification number: H01L27/092 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/7848

Abstract: A transistor structure is provided in the present invention. The transistor structure includes: a substrate comprising a P-type well, a gate disposed on the P-type well, a first spacer disposed on the gate, an N-type source/drain region disposed in the substrate at two sides of the gate, a silicon cap layer covering the N-type source/drain region, a second spacer around the first spacer and the second spacer directly on and covering a portion of the silicon cap layer and a silicide layer disposed on the silicon cap layer.

Abstract translation: 在本发明中提供一种晶体管结构。 晶体管结构包括：包括P型阱的衬底，设置在P型阱上的栅极，设置在栅极上的第一间隔物，设置在栅极两侧的衬底中的N型源极/漏极区域 覆盖N型源极/漏极区域的硅覆盖层，围绕第一间隔物的第二间隔物和第二间隔物，直接覆盖硅覆盖层的一部分并且覆盖硅覆盖层上的硅化物层。

公开(公告)号：US08183640B2

公开(公告)日：2012-05-22

申请号：US12502239

申请日：2009-07-14

Applicant: Wen-Han Hung ,  Tsai-Fu Chen ,  Shyh-Fann Ting ,  Cheng-Tung Huang ,  Kun-Hsien Lee ,  Ta-Kang Lo ,  Tzyy-Ming Cheng

Inventor： Wen-Han Hung ,  Tsai-Fu Chen ,  Shyh-Fann Ting ,  Cheng-Tung Huang ,  Kun-Hsien Lee ,  Ta-Kang Lo ,  Tzyy-Ming Cheng

IPC: H01L29/76 ,  H01L29/94

CPC classification number: H01L27/092 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/7848

Abstract: A method of fabricating transistors includes: providing a substrate including an N-type well and P-type well; forming a first gate on the N-type well and a second gate on the P-type well, respectively; forming a third spacer on the first gate; forming an epitaxial layer in the substrate at two sides of the first gate; forming a fourth spacer on the second gate; forming a silicon cap layer covering the surface of the epitaxial layer and the surface of the substrate at two sides of the fourth spacer; and forming a first source/drain doping region and a second source/drain doping region at two sides of the first gate and the second gate respectively.

Abstract translation: 制造晶体管的方法包括：提供包括N型阱和P型阱的衬底; 在N型阱上分别形成第一栅极和P型阱上的第二栅极; 在所述第一门上形成第三间隔物; 在第一栅极的两侧在衬底中形成外延层; 在所述第二闸门上形成第四间隔物; 在所述第四间隔物的两侧形成覆盖所述外延层的表面和所述基板的表面的硅覆盖层; 以及分别在所述第一栅极和所述第二栅极的两侧形成第一源极/漏极掺杂区域和第二源极/漏极掺杂区域。

公开(公告)号：US20120009745A1

公开(公告)日：2012-01-12

申请号：US12983894

申请日：2011-01-04

Applicant: Kun-Hsien Lee ,  Cheng-Tung Huang ,  Wen-Han Hung ,  Shyh-Fann Ting ,  Li-Shian Jeng ,  Meng-Yi Wu ,  Tzyy-Ming Cheng

Inventor： Kun-Hsien Lee ,  Cheng-Tung Huang ,  Wen-Han Hung ,  Shyh-Fann Ting ,  Li-Shian Jeng ,  Meng-Yi Wu ,  Tzyy-Ming Cheng

IPC: H01L21/8238

CPC classification number: H01L21/26506 ,  H01L21/26513 ,  H01L21/2658 ,  H01L21/26586 ,  H01L29/1083 ,  H01L29/6659 ,  H01L29/7833

Abstract: A method for fabricating complimentary metal-oxide-semiconductor field-effect transistor is disclosed. The method includes the steps of: (A) forming a first gate structure and a second gate structure on a substrate; (B) performing a first co-implantation process to define a first type source/drain extension region depth profile in the substrate adjacent to two sides of the first gate structure; (C) forming a first source/drain extension region in the substrate adjacent to the first gate structure; (D) performing a second co-implantation process to define a first pocket region depth profile in the substrate adjacent to two sides of the second gate structure; (E) performing a first pocket implantation process to form a first pocket region adjacent to two sides of the second gate structure.

Abstract translation: 公开了一种用于制造互补金属氧化物半导体场效应晶体管的方法。 该方法包括以下步骤：（A）在衬底上形成第一栅极结构和第二栅极结构; （B）执行第一共注入工艺以限定与所述第一栅极结构的两侧相邻的所述衬底中的第一类型源极/漏极延伸区域深度分布; （C）在与第一栅极结构相邻的衬底中形成第一源极/漏极延伸区域; （D）执行第二共注入工艺以限定与所述第二栅极结构的两侧相邻的所述衬底中的第一袋区深度分布; （E）执行第一口袋注入工艺以形成与第二栅极结构的两侧相邻的第一袋区域。