公开(公告)号：US06255203B1

公开(公告)日：2001-07-03

申请号：US09216672

申请日：1998-12-16

Applicant: Huang-Chung Cheng ,  Wen-Koi Lai ,  Nan-Ching Chen

Inventor： Huang-Chung Cheng ,  Wen-Koi Lai ,  Nan-Ching Chen

IPC: H01L2120

CPC classification number: H01L29/665 ,  H01L21/28052 ,  H01L29/4933

Abstract: This application relates to a process to suppress the impurity diffusion through gate oxide on silicided amorphous-Si gate structures that utilize the silicide layers as the implantation barrier to minimize the impurity diffusion by reducing the projectile range and implant-induced defects, resulting in smaller flat-band voltage(VFB) shift and better characteristics of the breakdown field(Ebd) and charge to breakdown(Qbd). In addition, the amorphous-Si underlying layer is simultaneously kept during the formation of a low-temperature self-aligned silicide (SAD) process to further retard the impurity diffusion. Hence, the usage of such bilayered silicide/amorphous-Si films could effectively retard the impurity diffusion, by combining both effects of the amorphous-Si layer and the silicide process or inducing other undesirable effects such as the increase of gate sheet resistance.

Abstract translation: 本申请涉及一种通过硅化非晶Si栅极结构抑制杂质扩散的方法，其利用硅化物层作为注入势垒，通过减少抛射体范围和植入物引起的缺陷来最小化杂质扩散，导致较小的平面 带状电压（VFB）偏移和更好的击穿场（Ebd）特性和击穿电荷（Qbd）。 此外，在形成低温自对准硅化物（SAD）工艺期间，同时保持非晶Si下层，以进一步延缓杂质扩散。 因此，这种双层硅化物/非晶硅膜的使用可以通过组合非晶硅层和硅化物工艺的两种效应或引起其他不期望的影响，例如增加栅极薄层电阻，来有效地延缓杂质扩散。

公开(公告)号：US07250332B2

公开(公告)日：2007-07-31

申请号：US10711038

申请日：2004-08-19

Applicant: Wen-Koi Lai ,  Tung-Hsing Lee ,  Tai-Yuan Lee ,  Yu-Lung Chin ,  Yi-Chia Lee ,  Shyh-Fann Ting

Inventor： Wen-Koi Lai ,  Tung-Hsing Lee ,  Tai-Yuan Lee ,  Yu-Lung Chin ,  Yi-Chia Lee ,  Shyh-Fann Ting

IPC: H01L21/8238

CPC classification number: H01L21/823864 ,  H01L21/26586 ,  H01L21/823814 ,  H01L21/84 ,  H01L29/6659

Abstract: The present invention discloses a method for fabricating a semiconductor device. A substrate is provided. At least one first and second gate structure, having sidewalls, are included on a surface of the substrate. A first ion implantation process is performed to form a shallow-junction doping region of a first conductive type in the substrate next to each of the sidewalls of the first gate structure, followed by the formation of offset spacers on each of the sidewalls of the first and second gate structure. A second ion implantation process is performed to form a shallow-junction doping region of a second conductive type in the substrate next to the offset spacer on each of the sidewalls of the second gate structure.

Abstract translation: 本发明公开了一种半导体器件的制造方法。 提供基板。 具有侧壁的至少一个第一和第二栅极结构被包括在基板的表面上。 执行第一离子注入工艺以在基板中的第一栅极结构的每个侧壁旁边形成第一导电类型的浅结掺杂区域，随后在第一栅极结构的每个侧壁上形成偏置间隔物 和第二门结构。 执行第二离子注入工艺以在第二栅极结构的每个侧壁上的偏移间隔物旁边的衬底中形成第二导电类型的浅结掺杂区域。

公开(公告)号：US20060040448A1

公开(公告)日：2006-02-23

申请号：US10711038

申请日：2004-08-19

Applicant: Wen-Koi Lai ,  Tung-Hsing Lee ,  Tai-Yuan Lee ,  Yu-Lung Chin ,  Yi-Chia Lee ,  Shyh-Fann Ting

Inventor： Wen-Koi Lai ,  Tung-Hsing Lee ,  Tai-Yuan Lee ,  Yu-Lung Chin ,  Yi-Chia Lee ,  Shyh-Fann Ting

IPC: H01L21/336

CPC classification number: H01L21/823864 ,  H01L21/26586 ,  H01L21/823814 ,  H01L21/84 ,  H01L29/6659

Abstract: The present invention discloses a method for fabricating a semiconductor device. A substrate is provided. At least one first and second gate structure, having sidewalls, are included on a surface of the substrate. A first ion implantation process is performed to form a shallow-junction doping region of a first conductive type in the substrate next to each of the sidewalls of the first gate structure, followed by the formation of offset spacers on each of the sidewalls of the first and second gate structure. A second ion implantation process is performed to form a shallow-junction doping region of a second conductive type in the substrate next to the offset spacer on each of the sidewalls of the second gate structure.

Abstract translation: 本发明公开了一种半导体器件的制造方法。 提供基板。 具有侧壁的至少一个第一和第二栅极结构被包括在基板的表面上。 执行第一离子注入工艺以在基板中的第一栅极结构的每个侧壁旁边形成第一导电类型的浅结掺杂区域，随后在第一栅极结构的每个侧壁上形成偏置间隔物 和第二门结构。 执行第二离子注入工艺以在第二栅极结构的每个侧壁上的偏移间隔物旁边的衬底中形成第二导电类型的浅结掺杂区域。