公开(公告)号：US07885782B2

公开(公告)日：2011-02-08

申请号：US11582141

申请日：2006-10-17

申请人： Raymond J. Beffa

发明人： Raymond J. Beffa

IPC分类号： G01R31/00 ,  G01R31/14 ,  G01N37/00

CPC分类号： H01L22/20 ,  G01R31/2894 ,  G06F11/006 ,  H01L21/67294 ,  H01L23/544 ,  H01L2223/54433 ,  H01L2223/5444 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of manufacturing IC devices from semiconductor wafers includes providing the wafers and fabricating ICs on the wafers. At probe, a unique fuse ID is stored in each IC, and an electronic wafer map is electronically stored for each wafer indicating the locations of good and bad ICs on the wafer and the fuse IDs of the ICs on the wafer. Each IC is then separated from its wafer to form an IC die, and the IC dice are assembled into IC devices. At the opens/shorts test at the end of assembly, the fuse ID of each IC in each device is automatically retrieved so the wafer map of the IC device may be accessed and evaluated to identify any IC devices containing bad ICs that have accidentally been assembled into IC devices. Any “bad” IC devices are discarded while remaining IC devices continue on to back-end testing.

摘要翻译： 从半导体晶片制造IC器件的方法包括提供晶片并在晶片上制造IC。 在探针中，每个IC中存储唯一的熔丝ID，并且电子地存储用于每个晶片的电子晶片图，其指示晶片上的良好和不良IC的位置以及晶片上的IC的熔丝ID。 然后将每个IC与其晶片分离以形成IC管芯，并将IC管芯组装成IC器件。 在组装结束时的开/短测试中，自动检索每个设备中每个IC的熔丝ID，以便可以访问和评估IC器件的晶片映射，以识别包含意外组装的不良IC的任何IC器件 进入IC设备。 任何“坏”IC器件都会被丢弃，而剩余的IC器件继续进行后端测试。

公开(公告)号：US07567091B2

公开(公告)日：2009-07-28

申请号：US12017262

申请日：2008-01-21

申请人： Warren M. Farnworth ,  William K. Waller ,  Leland R. Nevill ,  Raymond J. Beffa ,  Eugene H. Cloud

发明人： Warren M. Farnworth ,  William K. Waller ,  Leland R. Nevill ,  Raymond J. Beffa ,  Eugene H. Cloud

IPC分类号： G01R31/26

CPC分类号： G01R31/025 ,  G01R31/2884

摘要： A circuit for isolating a short-circuited integrated circuit (IC) formed on the surface of a semiconductor wafer from other ICs formed on the wafer that are interconnected with the short-circuited IC includes control circuitry within the short-circuited IC for sensing the short circuit. The control circuitry may sense the short circuit in a variety of ways, including sensing excessive current drawn by the short-circuited IC, and sensing an abnormally low or high voltage within the short-circuited IC. Switching circuitry also within the short-circuited IC selectively isolates the short-circuited IC from the other ICs on the wafer in response to the control circuitry sensing the short circuit. As a result, if the wafer is under probe test, for example, testing can continue uninterrupted on the other ICs while the short-circuited IC is isolated.

摘要翻译： 用于将形成在半导体晶片的表面上的短路集成电路（IC）与形成在晶片上的与短路IC互连的其他IC隔离的电路包括用于感测短路IC的短路IC内的控制电路 电路。 控制电路可以以各种方式感测短路，包括感测由短路IC吸引的过电流，以及感测短路IC内的异常低或高电压。 短路IC内的开关电路响应于控制电路感测短路而选择性地将短路IC与晶片上的其它IC隔离。 结果，如果晶片处于探针测试之下，例如，在短路IC隔离的同时，其它IC上的测试可以不中断地继续。

公开(公告)号：US20090060703A1

公开(公告)日：2009-03-05

申请号：US12248368

申请日：2008-10-09

申请人： Raymond J. Beffa

发明人： Raymond J. Beffa

IPC分类号： H01L21/67

CPC分类号： B07C5/3412 ,  B07C5/344 ,  G01R31/2851 ,  H01L23/544 ,  H01L2223/5444 ,  H01L2223/54473 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for sorting integrated circuit (IC) devices of the type having a substantially unique identification (ID) code, such as a fuse ID, including automatically reading the ID code of each of the IC devices and sorting the IC devices in accordance with their automatically read ID codes, is disclosed.

摘要翻译： 一种用于分类具有基本上唯一的识别（ID）代码（诸如熔丝ID）的集成电路（IC）装置的方法，其包括自动读取每个IC器件的ID码并根据它们对IC器件进行分类 自动读取ID码，被披露。

公开(公告)号：US07489564B2

公开(公告)日：2009-02-10

申请号：US11452819

申请日：2006-06-14

申请人： Brent Keeth ,  Layne G. Bunker ,  Raymond J. Beffa ,  Frank F. Ross

发明人： Brent Keeth ,  Layne G. Bunker ,  Raymond J. Beffa ,  Frank F. Ross

IPC分类号： G11C11/00

CPC分类号： G11C5/063 ,  G11C5/025 ,  G11C5/145 ,  G11C5/147 ,  G11C11/401 ,  G11C11/4074 ,  G11C11/4076 ,  G11C11/4097 ,  G11C11/4099 ,  G11C29/021 ,  G11C29/028 ,  G11C29/12 ,  G11C29/12005 ,  G11C29/46 ,  G11C29/787 ,  G11C2029/0407 ,  H01L27/10805 ,  H01L2224/4826 ,  H01L2224/73215 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/00

摘要： A 256 Meg dynamic random access memory is comprised of a plurality of cells organized into individual arrays, with the arrays being organized into 32 Meg array blocks, which are organized into 64 Meg quadrants. Sense amplifiers are positioned between adjacent rows in the individual arrays while row decoders are positioned between adjacent columns in the individual arrays. In certain of the gap cells, multiplexers are provided to transfer signals from I/O lines to datalines. A data path is provided which, in addition to the foregoing, includes array I/O blocks, responsive to the datalines from each quadrant to output data to a data read mux, data buffers, and data driver pads. The write data path includes a data in buffer and data write muxes for providing data to the array I/O blocks. A power bus is provided which minimizes routing of externally supplied voltages, completely rings each of the array blocks, and provides gridded power distribution within each of the array blocks. A plurality of voltage supplies provide the voltages needed in the array and in the peripheral circuits. The power supplies are organized to match their power output to the power demand and to maintain a desired ratio of power production capability and decoupling capacitance. A powerup sequence circuit is provided to control the powerup of the chip. Redundant rows and columns are provided as is the circuitry necessary to logically replace defective rows and columns with operational rows and columns. Circuitry is also provided on chip to support various types of test modes.

摘要翻译： 一个256兆赫动态随机存取存储器由组成单独阵列的多个单元组成，阵列被组织成32兆赫阵列阵列，它们被组织成64兆象限。 感测放大器位于各个阵列中的相邻行之间，而行解码器位于各个阵列中的相邻列之间。 在某些间隙单元中，提供多路复用器以将信号从I / O线传送到数据线。 提供了一种数据路径，除了上述之外，还包括阵列I / O块，响应于来自每个象限的数据，将数据输出到数据读取复用器，数据缓冲器和数据驱动器焊盘。 写数据路径包括用于向阵列I / O块提供数据的缓冲器和数据写入多路复用器中的数据。 提供电源总线，其最小化外部提供的电压的路由，完全环绕每个阵列块，并且在每个阵列块内提供网格化的功率分配。 多个电压源提供阵列和外围电路中所需的电压。 电源组合以将其功率输出与功率需求相匹配，并保持所需的功率生产能力和去耦电容的比例。 提供上电序列电路以控制芯片的上电。 提供了冗余的行和列，就像使用操作行和列逻辑地替换有缺陷的行和列所需的电路一样。 芯片上还提供电路以支持各种类型的测试模式。

公开(公告)号：US07368678B2

公开(公告)日：2008-05-06

申请号：US10218380

申请日：2002-08-13

申请人： Raymond J. Beffa

发明人： Raymond J. Beffa

IPC分类号： B07C5/344

CPC分类号： B07C5/344 ,  B07C5/3412 ,  G01R31/01 ,  G01R31/2851 ,  H01L2223/5444 ,  H01L2223/54473

摘要： A method for sorting integrated circuit (IC) devices of the type having a substantially unique identification (ID) code, such as a fuse ID, including automatically reading the ID code of each of the IC devices and sorting the IC devices in accordance with their automatically read ID codes, is disclosed.

摘要翻译： 一种用于分类具有基本上唯一的识别（ID）代码（诸如熔丝ID）的集成电路（IC）装置的方法，其包括自动读取每个IC器件的ID码并根据它们对IC器件进行分类 自动读取ID码，被披露。

公开(公告)号：US07124050B2

公开(公告)日：2006-10-17

申请号：US11150752

申请日：2005-06-10

申请人： Raymond J. Beffa

发明人： Raymond J. Beffa

IPC分类号： G06F19/00 ,  G06G7/6466

CPC分类号： H01L22/20 ,  G01R31/2894 ,  G06F11/006 ,  H01L21/67294 ,  H01L23/544 ,  H01L2223/54433 ,  H01L2223/5444 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of manufacturing IC devices from semiconductor wafers includes providing the wafers and fabricating ICs on the wafers. At probe, a unique fuse ID is stored in each IC, and an electronic wafer map is electronically stored for each wafer indicating the locations of good and bad ICs on the wafer and the fuse IDs of the ICs on the wafer. Each IC is then separated from its wafer to form an IC die, and the IC dice are assembled into IC devices. At the opens/shorts test at the end of assembly, the fuse ID of each IC in each device is automatically retrieved so the wafer map of the IC device may be accessed and evaluated to identify any IC devices containing bad ICs that have accidentally been assembled into IC devices. Any “bad” IC devices are discarded while remaining IC devices continue on to back-end testing.

摘要翻译： 从半导体晶片制造IC器件的方法包括提供晶片并在晶片上制造IC。 在探针中，每个IC中存储唯一的熔丝ID，并且电子地存储用于每个晶片的电子晶片图，其指示晶片上的良好和不良IC的位置以及晶片上的IC的熔丝ID。 然后将每个IC与其晶片分离以形成IC管芯，并将IC管芯组装成IC器件。 在组装结束时的开/短测试中，自动检索每个设备中每个IC的熔丝ID，以便可以访问和评估IC器件的晶片映射，以识别包含意外组装的不良IC的任何IC器件 进入IC设备。 任何“坏”IC器件都会被丢弃，而剩余的IC器件继续进行后端测试。

公开(公告)号：US06350959B1

公开(公告)日：2002-02-26

申请号：US09520067

申请日：2000-03-07

申请人： Raymond J. Beffa

发明人： Raymond J. Beffa

IPC分类号： B07C5344

CPC分类号： B07C5/3412 ,  B07C5/344 ,  G01R31/2851 ,  H01L23/544 ,  H01L2223/5444 ,  H01L2223/54473 ,  H01L2924/0002 ,  H01L2924/00

摘要： An inventive method for sorting integrated circuit (IC) devices of the type having a substantially unique identification (ID) code, such as a fuse ID, includes automatically reading the ID code of each of the IC devices, and sorting the IC devices in accordance with their automatically read ID codes. The inventive method can be used in conjunction with an IC manufacturing process that includes providing semiconductor wafers, fabricating the IC's on each of the wafers, causing each of the IC's to store its ID code, separating each of the IC's from its wafer to form IC dice, assembling the IC dice into IC devices, and testing the IC devices. The inventive method is useful for, among other things, culling IC reject bins for shippable IC's, sorting IC's from a wafer lot into those that require enhanced reliability testing and those that do not, and allowing IC's fabricated using both a control fabrication process recipe and a new fabrication process recipe under test to be assembled and tested using the same equipment to reduce unintended test variables introduced when the IC's are assembled and tested separately.

摘要翻译： 用于排列具有基本上唯一的识别（ID）代码（诸如熔丝ID）的类型的集成电路（IC）设备的创新方法包括自动读取每个IC设备的ID代码，以及按照 并自动读取ID码。 本发明的方法可以与IC制造工艺结合使用，该IC制造工艺包括提供半导体晶片，在每个晶片上制造IC，使IC中的每一个存储其ID代码，将IC中的每一个与其晶片分离以形成IC 骰子，将IC骰子组装到IC器件中，并对IC器件进行测试。 本发明的方法尤其可用于剔除可运输IC的IC拒收箱，将IC从晶片批量分类为需要增强的可靠性测试的IC和不允许使用控制制造工艺配方的IC制造的IC 使用相同的设备组装和测试的新的制造工艺配方，以减少IC独立组装和测试时引入的意外测试变量。

公开(公告)号：US06313658B1

公开(公告)日：2001-11-06

申请号：US09083819

申请日：1998-05-22

申请人： Warren M. Farnworth ,  William K. Waller ,  Leland R. Nevill ,  Raymond J. Beffa ,  Eugene H. Cloud

发明人： Warren M. Farnworth ,  William K. Waller ,  Leland R. Nevill ,  Raymond J. Beffa ,  Eugene H. Cloud

IPC分类号： G01R3126

CPC分类号： G01R31/025 ,  G01R31/2884

摘要： A circuit for isolating a short-circuited integrated circuit (IC) formed on the surface of a semiconductor wafer from other ICs formed on the wafer that are interconnected with the short-circuited IC includes control circuitry within the short-circuited IC for sensing the short circuit. The control circuitry may sense the short circuit in a variety of ways, including sensing excessive current drawn by the short-circuited IC, and sensing an abnormally low or high voltage within the short-circuited IC. Switching circuitry also within the short-circuited IC selectively isolates the short-circuited IC from the other ICs on the wafer in response to the control circuitry sensing the short circuit. As a result, if the wafer is under probe test, for example, testing can continue uninterrupted on the other ICs while the short-circuited IC is isolated.

摘要翻译： 用于将形成在半导体晶片的表面上的短路集成电路（IC）与形成在晶片上的与短路IC互连的其他IC隔离的电路包括用于感测短路IC的短路IC内的控制电路 电路。 控制电路可以以各种方式感测短路，包括感测由短路IC吸引的过电流，以及感测短路IC内的异常低或高电压。 短路IC内的开关电路响应于控制电路感测短路而选择性地将短路IC与晶片上的其它IC隔离。 结果，如果晶片处于探针测试之下，例如，在短路IC隔离的同时，其它IC上的测试可以不中断地继续。

公开(公告)号：US6147316A

公开(公告)日：2000-11-14

申请号：US133336

申请日：1998-08-13

申请人： Raymond J. Beffa

发明人： Raymond J. Beffa

IPC分类号： B07C5/34 ,  B07C5/344 ,  G01R31/01 ,  G01R31/28

CPC分类号： B07C5/344 ,  B07C5/3412 ,  G01R31/01 ,  G01R31/2851 ,  H01L2223/5444 ,  H01L2223/54473

摘要： An inventive method for sorting integrated circuit (IC) devices of the type having a substantially unique identification (ID) code, such as a fuse ID, includes automatically reading the ID code of each of the IC devices, and sorting the IC devices in accordance with their automatically read ID codes. The inventive method can be used in conjunction with an IC manufacturing process that includes providing semiconductor wafers, fabricating the IC's on each of the wafers, causing each of the IC's to store its ID code, separating each of the IC's from its wafer to form IC dice, assembling the IC dice into IC devices, and testing the IC devices. The inventive method is useful for, among other things, culling IC reject bins for shippable IC's, sorting IC's from a wafer lot into those that require enhanced reliability testing and those that do not, and allowing IC's fabricated using both a control fabrication process recipe and a new fabrication process recipe under test to be assembled and tested using the same equipment to reduce unintended test variables introduced when the IC's are assembled and tested separately.

公开(公告)号：US5994915A

公开(公告)日：1999-11-30

申请号：US994844

申请日：1997-12-19

申请人： Warren M. Farnworth ,  Leland R. Nevill ,  Raymond J. Beffa ,  Eugene H. Cloud

发明人： Warren M. Farnworth ,  Leland R. Nevill ,  Raymond J. Beffa ,  Eugene H. Cloud

IPC分类号： G01R31/02 ,  G01R31/26 ,  G01R31/28 ,  G01R31/317 ,  G01R31/3185 ,  H01L21/00 ,  H01L21/8238 ,  H01L23/58 ,  H01L27/10 ,  H01L29/00

CPC分类号： G01R31/2868 ,  G01R31/2841 ,  G01R31/2856 ,  G01R31/31701 ,  G01R31/318505 ,  G01R31/318511 ,  G11C29/1201 ,  G11C29/48 ,  G01R31/2831 ,  G01R31/2855 ,  H01L22/32 ,  H01L2924/0002

摘要： A semiconductor wafer having dice that include circuitry that is placed into a mode when the circuitry receives an alternating signal having certain characteristics. The alternating signal may be supplied from a system controller through a probe, probe pad, and conductive path on the wafer. In a preferred embodiment, the conductive path simultaneously carries a VCC power signal and the alternating signal to the circuitry. However, the alternating signal may be carried on a conductive path different from the one carrying the VCC signal. A great deal of information may be conveyed through the alternating signal, making other signals unnecessary in controlling, testing, stressing, and repairing dice on the wafer. For example, clocking information may be conveyed through the alternating signal. The circuitry may be placed in different modes in response to different characteristics of the alternating signal. The alternating signal and a VCC power signal are received through a single contact on each die. A wafer mode controlling system includes a system controller to control application of the alternating signals and other signals to the dice on the wafer. The semiconductor wafer mode controlling system may also control a probe positioning controller including an array of probes that selectively brings the probes into contact with the probe pads, whereby the alternating signal having the certain characteristics is transmitted from the probe to the circuitry through the probe pad and conductive path and the circuitry of each of the dice is placed into the mode.