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    Bit line structure for semiconductor memory device with bank separation at cross-over regions
    42.
    发明授权
    Bit line structure for semiconductor memory device with bank separation at cross-over regions 失效
    半导体存储器件的位线结构，在交叉区域具有银行分离

    公开(公告)号：US5461589A

    公开(公告)日：1995-10-24

    申请号：US145733

    申请日：1993-11-04

    Applicant: Hideto Hidaka ,  Kazuyasu Fujishima ,  Yoshio Matsuda

    Inventor： Hideto Hidaka ,  Kazuyasu Fujishima ,  Yoshio Matsuda

    IPC: G11C5/06 ,  G11C7/18 ,  G11C7/02

    CPC classification number: G11C5/063 ,  G11C7/18

    Abstract: A semiconductor memory device of folded bit line structure provided with a cross portion in at least one portion of each of bit line pairs so that values of coupling capacitance with adjacent bit line pairs are equal to each other with respect to the paired bit lines.Preferably, the respective bit line pairs are equally divided into 4N and the cross parts are provided at dividing points so that bit line pairs having the cross parts at the same dividing points are arranged on alternate pairs of bit lines.Preferably, the cross parts are provided in regions for forming restore circuits or sense amplifiers.More preferably, a dummy word line for selecting dummy cells for providing reference potential is selected by the position of a selected word line.

    Abstract translation: 一种折叠位线结构的半导体存储器件，其在位线对中的每一个的至少一部分中具有交叉部分，使得与相邻位线对的耦合电容值相对于成对位线彼此相等。 优选地，各位线对被等分成4N，并且在分割点处提供交叉部分，使得在相同分割点处具有交叉部分的位线对被布置在交替的位线对上。 优选地，十字部分设置在用于形成恢复电路或感测放大器的区域中。 更优选地，通过所选字线的位置选择用于选择用于提供参考电位的虚拟单元的虚拟字线。

    Bit line structure for semiconductor memory device
    43.
    发明授权
    Bit line structure for semiconductor memory device 失效
    半导体存储器件的位线结构

    公开(公告)号：US5280443A

    公开(公告)日：1994-01-18

    申请号：US028906

    申请日：1993-03-08

    Applicant: Hideto Hidaka ,  Kazuyasu Fujishima ,  Yoshio Matsuda

    Inventor： Hideto Hidaka ,  Kazuyasu Fujishima ,  Yoshio Matsuda

    IPC: G11C5/06 ,  G11C7/18

    CPC classification number: G11C5/063 ,  G11C7/18

    Abstract: A semiconductor memory device of folded bit line structure provided with a cross portion in at least one portion of each of bit line pairs so that values of coupling capacitance with adjacent bit line pairs are equal to each other with respect to the paired bit lines. Preferably, the respective bit line pairs are equally divided into 4N and the cross parts are provided at dividing points so that bit line pairs having the cross parts at the same dividing points are arranged on alternate pairs of bit lines. Preferably, the cross parts are provided in regions for forming restore circuits or sense amplifiers. More preferably, a dummy word line for selecting dummy cells for providing reference potential is selected by the position of a selected word line.

    Abstract translation: 一种折叠位线结构的半导体存储器件，其在位线对中的每一个的至少一部分中具有交叉部分，使得与相邻位线对的耦合电容值相对于成对位线彼此相等。 优选地，各位线对被等分成4N，并且在分割点处提供交叉部分，使得在相同分割点处具有交叉部分的位线对被布置在交替的位线对上。 优选地，十字部分设置在用于形成恢复电路或感测放大器的区域中。 更优选地，通过所选字线的位置选择用于选择用于提供参考电位的虚拟单元的虚拟字线。

    Method for manufacturing semiconductor memory device having stacked memory capacitors
    45.
    发明授权
    Method for manufacturing semiconductor memory device having stacked memory capacitors 失效
    具有层叠存储电容器的半导体存储器件的制造方法

    公开(公告)号：US5250458A

    公开(公告)日：1993-10-05

    申请号：US793971

    申请日：1991-11-18

    Applicant: Katsuhiro Tsukamoto ,  Masahiro Shimizu ,  Kazuyasu Fujishima ,  Yoshio Matsuda

    Inventor： Katsuhiro Tsukamoto ,  Masahiro Shimizu ,  Kazuyasu Fujishima ,  Yoshio Matsuda

    IPC: G11C11/404 ,  H01L21/334 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/417 ,  H01L29/78 ,  H01L29/92

    CPC classification number: H01L27/10861 ,  G11C11/404 ,  H01L27/10829 ,  H01L29/41725 ,  H01L29/41766 ,  H01L29/66181

    Abstract: A dynamic RAM comprises an array of memory cells, each of the memory cells comprising a single access transistor and a charge storage region. The charge storage region comprises a first capacitor memory including a P.sup.+ region serving as an opposite electrode formed in the inner surface of a trench formed in a P type silicon substrate, a first capacitor dielectric film formed on the P.sup.+ region and a common electrode layer serving as a memory terminal formed on the first capacitor dielectric film, and a second memory capacitor including the common electrode layer, a second capacitor dielectric film formed on the common electrode layer and a cell plate electrode formed on the second capacitor dielectric film. The memory terminal and a drain region of the access transistor are connected in a self-aligning manner by an electrode having a sidewall shape which is in contact with an end of the memory terminal. Thus, a contact hole need not be formed in the first capacitor dielectric film, so that decrease of the electrical reliability of the first capacitor dielectric film can be prevented. The drain region of the access transistor may be formed by self-alignment with the contact portion of the common electrode layer.

    Abstract translation: 动态RAM包括存储器单元的阵列，每个存储器单元包括单个存取晶体管和电荷存储区域。 电荷存储区域包括第一电容器存储器，其包括形成在形成于P型硅衬底中的沟槽的内表面中的用作相对电极的P +区，形成在P +区上的第一电容器电介质膜和用于 作为形成在第一电容器电介质膜上的存储器端子，以及包括公共电极层的第二存储电容器，形成在公共电极层上的第二电容器电介质膜和形成在第二电容器电介质膜上的单元板电极。 存取晶体管的存储器端子和漏极区域通过具有与存储器端子的端部接触的侧壁形状的电极以自对准的方式连接。 因此，不需要在第一电容器电介质膜中形成接触孔，从而可以防止第一电容器电介质膜的电可靠性的降低。 存取晶体管的漏极区可以通过与公共电极层的接触部分进行自对准而形成。

    Method for manufacturing semiconductor memory device having improved resistance to .alpha. particle induced soft errors
    46.
    发明授权
    Method for manufacturing semiconductor memory device having improved resistance to .alpha. particle induced soft errors 失效
    具有改善的抵抗α粒子诱导的软错误的半导体存储器件的制造方法

    公开(公告)号：US5030586A

    公开(公告)日：1991-07-09

    申请号：US282803

    申请日：1988-12-12

    Applicant: Yoshio Matsuda ,  Kazuyasu Fujishima

    Inventor： Yoshio Matsuda ,  Kazuyasu Fujishima

    IPC: H01L27/10 ,  H01L21/8242 ,  H01L27/108

    CPC classification number: H01L27/1085 ,  H01L27/10805

    Abstract: In the semiconductor memory device according to the present invention, a n type drain diffused region (9a) to be connected to a bit line (12) is formed on a p type semiconductor substrate (1) and a n type source diffused region (9b) is formed with a prescribed spacing from the n type drain region (9a). On the p type silicon substrate (1), a p type diffused region (16a) of high impurity density and p type diffused region (16b) of high impurity density are formed in such a manner that they are in contact with the n type drain diffused region (9a) and the n type source diffused region (9b), respectively, but not in the channel region of the n channel MOS transistor (18). Consequently, the .alpha. particle-generated charges can be decreased without changing the threshold voltage of the transfer gate transistor.

    Test signal generator for semiconductor integrated circuit memory and testing method thereof
    47.
    发明授权
    Test signal generator for semiconductor integrated circuit memory and testing method thereof 失效
    半导体集成电路存储器的测试信号发生器及其测试方法

    公开(公告)号：US5022007A

    公开(公告)日：1991-06-04

    申请号：US506616

    申请日：1990-04-10

    Applicant: Kazutami Arimoto ,  Yoshio Matsuda ,  Tsukasa Ooishi ,  Masaki Tsukude ,  Kazuyasu Fujishima

    Inventor： Kazutami Arimoto ,  Yoshio Matsuda ,  Tsukasa Ooishi ,  Masaki Tsukude ,  Kazuyasu Fujishima

    IPC: G11C11/401 ,  G11C11/409 ,  G11C29/00 ,  G11C29/10 ,  G11C29/12 ,  G11C29/34 ,  G11C29/56

    CPC classification number: G11C29/56 ,  G11C29/34

    Abstract: A test signal generator for a semiconductor integrated circuit memory, wherein when transfer transistors (20, 21, 14, 15) are rendered conductive, a test data cloumn is supplied from an I/O line pair (11, 12) to a column of a register (10) and stored therein. When a transfer (67) is rendered conductive, the test data column written in the register is written in a column of a memory cell (22) in the same pattern and when transfer transistors (16, 17) are rendered conductive, the test data column written in the register is inverted and the, written in the memory cell column, Data in the memory cell column is read out by a word line (13) and amplified by a sense amplifier (5), so that the data and the test data stored in the register are compared by a coincidence detection circuit 8 to detect whether it is coincident or not.

    Abstract translation: 一种用于半导体集成电路存储器的测试信号发生器，其中当传输晶体管（20,21,14,15）导通时，测试数据线从I / O线对（11,12）提供到 寄存器（10）并存储在其中。 当传送（67）导通时，写入寄存器的测试数据列以相同的模式写入存储单元（22）的列中，并且当传输晶体管（16,17）导通时，测试数据 写入寄存器的列被反相，并且写入存储单元列中，存储单元列中的数据被字线（13）读出并由读出放大器（5）放大，使得数据和测试 存储在寄存器中的数据由重合检测电路8进行比较，以检测其是否一致。

    Bit line structure for a dynamic type semiconductor memory device
    48.
    发明授权
    Bit line structure for a dynamic type semiconductor memory device 失效
    动态型半导体存储器件的位线结构

    公开(公告)号：US5012447A

    公开(公告)日：1991-04-30

    申请号：US276741

    申请日：1988-11-28

    Applicant: Yoshio Matsuda ,  Kazuyasu Fujishima

    Inventor： Yoshio Matsuda ,  Kazuyasu Fujishima

    IPC: G11C11/401 ,  G11C5/06 ,  G11C11/4097

    CPC classification number: G11C5/063 ,  G11C11/4097

    Abstract: Each of the bit lines constituting each of a plurality of bit line pairs included in a portion of a memory cell array comprises even-numbered intersecting portions. At the intersecting portion, the materials of respective bit lines are different from each other. The bit lines are formed of the same material at portions other than the intersecting portions. The intersecting portions are arranged such that one of the bit lines constituting each bit line pair neighbors one of the bit lines constituting an adjacent one of the bit line pairs for a first length and neighbors the other one of the bit lines constituting the adjacent bit line pair for a second length; and the other one of the bit lines constituting the bit line pair neighbors the one of the bit lines of the adjacent bit line pair for the first length and neighbors the other one of the bit lines of the adjacent bit line pair for the second length.

    Abstract translation: 包括在存储单元阵列的一部分中的多个位线对中的每一个的每个位线包括偶数相交部分。 在交叉部分，各位线的材料彼此不同。 位线在相交部分以外的部分由相同的材料形成。 相交部分被布置为使得构成每个位线对的位线之一与构成相邻一个位线对的位线之一第一长度相邻，并且与构成相邻位线的位线中的另一个相邻 配对第二个长度; 并且构成位线对的位线中的另一个与第一长度的相邻位线对的位线之一相邻，并且邻近第二长度的相邻位线对的位线的另一个。

    Cache memory system having error correcting circuit
    49.
    发明授权
    Cache memory system having error correcting circuit 失效
    具有纠错电路的高速缓冲存储器系统

    公开(公告)号：US4953164A

    公开(公告)日：1990-08-28

    申请号：US254233

    申请日：1988-10-06

    Applicant: Mikio Asakura ,  Kazuyasu Fujishima ,  Yoshio Matsuda

    Inventor： Mikio Asakura ,  Kazuyasu Fujishima ,  Yoshio Matsuda

    IPC: G11C11/413 ,  G06F11/10 ,  G06F12/08 ,  G11C11/401 ,  G11C29/00 ,  G11C29/42

    CPC classification number: G06F11/1064 ,  G06F12/0802

    Abstract: There are provided a first memory cell array and a second memory cell array. The first memory cell array comprises a dynamic RAM and the second memory cell array comprises a static RAM. In addition, the second memory cell array has smaller capacity than that of the first memory cell array. An error correcting circuit, a check bit generating circuit and a register are connected between the first memory cell array and the second memory cell array. Data which is frequently accessed is transferred from the first memory cell array to the second memory cell array and stored therein. Access is made to the second memory cell array. When data which is required is not in the second memory cell array, access is made to the first memory cell array. At the time of transferring data from the first memory cell array to the second memory cell array, errors are corrected by the error correcting circuit. The check bit generating circuit is responsive to data whose error is corrected by the error correcting circuit for generating new check bits.

    Abstract translation: 提供了第一存储单元阵列和第二存储单元阵列。 第一存储单元阵列包括动态RAM，第二存储单元阵列包括静态RAM。 此外，第二存储单元阵列具有比第一存储单元阵列小的容量。 纠错电路，校验位产生电路和寄存器连接在第一存储单元阵列和第二存储单元阵列之间。 频繁访问的数据从第一存储单元阵列传送到第二存储单元阵列并存储在其中。 访问第二个存储单元阵列。 当所需的数据不在第二存储单元阵列中时，对第一存储单元阵列进行访问。 在将数据从第一存储单元阵列传送到第二存储单元阵列时，错误校正电路校正错误。 校验位产生电路响应于错误被纠错电路校正的数据，用于产生新的校验位。

    Automated error detection for multiple block memory array chip and correction thereof
    50.
    发明授权
    Automated error detection for multiple block memory array chip and correction thereof 失效
    多块存储器阵列芯片的自动错误检测及其校正

    公开(公告)号：US4918692A

    公开(公告)日：1990-04-17

    申请号：US201413

    申请日：1988-06-02

    Applicant: Hideto Hidaka ,  Kazuyasu Fujishima ,  Yoshio Matsuda

    Inventor： Hideto Hidaka ,  Kazuyasu Fujishima ,  Yoshio Matsuda

    IPC: G11C29/00 ,  G06F11/10 ,  G11C11/401 ,  G11C29/04 ,  G11C29/42 ,  H01L27/10

    CPC classification number: G06F11/1008 ,  G06F11/1076

    Abstract: A semiconductor memory device comprises a plurality of memory cell array blocks. An address changing system is provided in each memory cell array block. The same address signal is applied to these address changing systems. Each address changing system comprises a plurality of linking devices. By previously blowing out any of the linking devices in each address changing system, an externally applied address signal is changed with another address signal to be applied to a corresponding memory cell array block.

    Abstract translation: 半导体存储器件包括多个存储单元阵列块。 在每个存储单元阵列块中提供地址改变系统。 相同的地址信号被应用于这些地址改变系统。 每个地址改变系统包括多个链接装置。 通过先前吹出每个地址改变系统中的任何链接装置，外部施加的地址信号被改变以应用于相应的存储单元阵列块的另一个地址信号。

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