公开(公告)号：US20090120679A1

公开(公告)日：2009-05-14

申请号：US12335605

申请日：2008-12-16

Applicant: Paul S. Andry ,  Chirag S. Patel ,  Edmund J. Sprogis ,  Cornelia K. Tsang

Inventor： Paul S. Andry ,  Chirag S. Patel ,  Edmund J. Sprogis ,  Cornelia K. Tsang

IPC: H01R12/22 ,  H01L21/768 ,  H05K3/42

CPC classification number: H01L23/49833 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49827 ,  H01L2221/68345 ,  H01L2224/0401 ,  H01L2224/05567 ,  H01L2224/13009 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/81191 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/12044 ,  H01L2924/3011 ,  Y10T29/49165 ,  H01L2924/014 ,  H01L2224/05552

Abstract: Conductive through vias are formed in electronic devices and electronic device carrier, such as, a silicon chip carrier. An annulus cavity is etched into the silicon carrier from the top side of the carrier and the cavity is filled with insulating material to form an isolation collar around a silicon core region. An insulating layer with at least one wiring level, having a portion in contact with the silicon core region, is formed on the top side of the carrier. Silicon is removed from the back side of the carrier sufficient to expose the distal portion of the isolation collar. The core region is etched out to expose the portion of the wiring level in contact with the silicon core region to form an empty via. The via is filled with conductive material in contact with the exposed portion of the wiring level to form a conductive through via to the wiring level. A solder bump formed, for example, from low melt C4 solder, is formed on the conductive via exposed on the carrier back side. The process acts to make the conductive via fill step independent of the via isolation step.

Abstract translation: 导电通孔形成在电子器件和电子器件载体中，例如硅芯片载体。 环状空腔从载体的顶侧蚀刻到硅载体中，并且空腔填充绝缘材料以在硅芯区域周围形成隔离环。 在载体的顶侧上形成具有至少一个布线层的绝缘层，其具有与硅芯区域接触的部分。 将硅从载体的背面移除，足以露出隔离套环的远端部分。 蚀刻芯区域以暴露与硅芯区域接触的布线层的部分以形成空通孔。 通孔填充有与布线层的暴露部分接触的导电材料，以形成导电通孔到布线层。 在载体背侧露出的导电通孔上形成例如由低熔点C4焊料形成的焊料凸块。 该过程用于使导电通孔填充步骤独立于通孔隔离步骤。

公开(公告)号：US20080268574A1

公开(公告)日：2008-10-30

申请号：US12035053

申请日：2008-02-21

Applicant: Kuan-Neng Chen ,  Bruce K. Furman ,  Edmund J. Sprogis ,  Anna W. Topol ,  Cornelia K. Tsang ,  Matthew R. Wordeman ,  Albert M. Young

Inventor： Kuan-Neng Chen ,  Bruce K. Furman ,  Edmund J. Sprogis ,  Anna W. Topol ,  Cornelia K. Tsang ,  Matthew R. Wordeman ,  Albert M. Young

IPC: H01L21/58

CPC classification number: H01L25/50 ,  H01L2224/80895 ,  H01L2225/06513 ,  H01L2225/06593 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A sealed microelectronic structure which provides mechanical stress endurance and includes at least two chips being electrically connected to a semiconductor structure at a plurality of locations. Each chip includes a continuous bonding material along it's perimeter and at least one support column connected to each of the chips positioned within the perimeter of each chip. Each support column extends outwardly such that when the at least two chips are positioned over one another the support columns are in mating relation to each other. A seal between the at least two chips results from the overlapping relation of the chip to one another such that the bonding material and support columns are in mating relation to each other. Thus, the seal is formed when the at least two chips are mated together, and results in a bonded chip structure.

Abstract translation: 一种密封的微电子结构，其提供机械应力耐久性并且包括在多个位置处电连接到半导体结构的至少两个芯片。 每个芯片沿着其周边包括连续的接合材料，以及连接到位于每个芯片的周边内的每个芯片的至少一个支撑柱。 每个支撑柱向外延伸，使得当至少两个芯片彼此定位时，支撑柱彼此配合。 至少两个芯片之间的密封由芯片彼此的重叠关系产生，使得接合材料和支撑柱彼此配合。 因此，当至少两个芯片配合在一起时形成密封，并且导致粘合芯片结构。

公开(公告)号：US20080176411A1

公开(公告)日：2008-07-24

申请号：US12056773

申请日：2008-03-27

Applicant: Raymond R. Horton ,  John U. Knickerbocker ,  Edmund J. Sprogis ,  Cornelia K. Tsang

Inventor： Raymond R. Horton ,  John U. Knickerbocker ,  Edmund J. Sprogis ,  Cornelia K. Tsang

IPC: H01L21/31

CPC classification number: H01L23/49827 ,  H01L23/49822 ,  H01L23/50 ,  H01L23/5382 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/01012 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/15311

Abstract: Techniques for electronic device fabrication are provided. In one aspect, an electronic device is provided. The electronic device comprises at least one interposer structure having one or mole vias and a plurality of decoupling capacitors integrated therein, the at least one interposer structure being configured to allow for one or more of the plurality of decoupling capacitors to be selectively deactivated. In another aspect, a method of fabricating an electronic device comprising at least one interposer structure having one or more vias and a plurality of decoupling capacitors integrated therein comprises the following step. One or more of the plurality of decoupling capacitors are selectively deactivated.

Abstract translation: 提供电子器件制造技术。 一方面，提供一种电子设备。 电子设备包括具有一个或多个通孔和集成在其中的多个去耦电容器的至少一个插入器结构，所述至少一个插入器结构被配置为允许选择性地去激活多个去耦电容器中的一个或多个。 在另一方面，一种制造电子器件的方法，包括至少一个具有一个或多个通孔的内插器结构和集成在其中的多个去耦电容器，其包括以下步骤。 选择性地去激活多个去耦电容器中的一个或多个。

公开(公告)号：US20080150147A1

公开(公告)日：2008-06-26

申请号：US12046737

申请日：2008-03-12

Applicant: James W. Adkisson ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Richard J. Rassel ,  Edmund J. Sprogis

Inventor： James W. Adkisson ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Richard J. Rassel ,  Edmund J. Sprogis

IPC: H01L23/488

CPC classification number: H01L24/02 ,  H01L23/3114 ,  H01L23/481 ,  H01L2224/0401 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/3011 ,  H01L2924/00

Abstract: A bond pad for effecting through-wafer connections to an integrated circuit or electronic package and method of producing thereof. The bond pad includes a high surface area aluminum bond pad in order to resultingly obtain a highly reliable, low resistance connection between bond pad and electrical leads.

Abstract translation: 用于实现通过晶片连接到集成电路或电子封装的接合焊盘及其制造方法。 接合焊盘包括高表面积铝键合焊盘，以便得到接合焊盘和电引线之间的高度可靠的低电阻连接。

公开(公告)号：US07189595B2

公开(公告)日：2007-03-13

申请号：US10771817

申请日：2004-06-16

Applicant: John H. Magerlein ,  Chirag S. Patel ,  Edmund J. Sprogis ,  Herbert I. Stoller

Inventor： John H. Magerlein ,  Chirag S. Patel ,  Edmund J. Sprogis ,  Herbert I. Stoller

IPC: H01L21/50

CPC classification number: H01L21/486 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/76898 ,  H01L23/147 ,  H01L24/16 ,  H01L2221/68318 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68345 ,  H01L2221/68354 ,  H01L2221/68363 ,  H01L2224/05571 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2224/0401 ,  H01L2924/00012

Abstract: A Silicon Based Package (SBP) is formed starting with a thick wafer, which serves as the base for the SBP, composed of silicon which has a first surface and a reverse surface which are planar. Then form an interconnection structure including metal capture structures in contact with the first surface and multilayer conductor patterns over the first surface. Form a temporary bond between the SBP and a wafer holder, with the wafer holder being a rigid structure. Thin the reverse side of the wafer to a desired thickness to form an Ultra Thin Silicon Wafer (UTSW) for the SBP. Form via holes with tapered or vertical sidewalls, which extend through the UTSW to reach the metal capture structures. Then form metal pads in the via holes which extend through the UTSW, making electrical contact to the metal capture structures. Then bond the metal pads in the via holes to pads of a carrier.

公开(公告)号：US06635970B2

公开(公告)日：2003-10-21

申请号：US10068537

申请日：2002-02-06

Applicant: Jerome B. Lasky ,  Edward J. Nowak ,  Edmund J. Sprogis

Inventor： Jerome B. Lasky ,  Edward J. Nowak ,  Edmund J. Sprogis

IPC: H01L2348

CPC classification number: H01L25/0657 ,  H01L23/481 ,  H01L23/50 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/00014 ,  H01L2924/00015 ,  H01L2924/01013 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05599 ,  H01L2224/85399 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A chip-on-chip module and associated method of formation. First and second semiconductor chips are coupled together. The first chip comprises a first wiring layer and a first electrically conductive substrate on first and second sides, respectively, of the first chip. A supply voltage VDD is adapted to be electrically coupled to the second side of the first chip. The second chip comprises a second wiring layer and a second electrically conductive substrate on first and second sides, respectively, of the second chip. A ground voltage GND is adapted to be electrically coupled to the second side of the second chip. The first side of the first chip is electrically coupled to the first side of the second chip. The supply voltage VDD and the ground voltage GND are adapted to provide power to the first and second chips.

Abstract translation: 片上芯片模块及相关的形成方法。 第一和第二半导体芯片被耦合在一起。 第一芯片包括分别在第一芯片的第一和第二侧上的第一布线层和第一导电基板。 电源电压VDD适于电耦合到第一芯片的第二侧。 第二芯片包括分别在第二芯片的第一和第二侧上的第二布线层和第二导电基板。 接地电压GND适于电耦合到第二芯片的第二侧。 第一芯片的第一侧电耦合到第二芯片的第一侧。 电源电压VDD和接地电压GND适于为第一和第二芯片提供电力。

公开(公告)号：US06265771B1

公开(公告)日：2001-07-24

申请号：US09238492

申请日：1999-01-27

Applicant: Thomas G. Ference ,  Wayne J. Howell ,  Edmund J. Sprogis

Inventor： Thomas G. Ference ,  Wayne J. Howell ,  Edmund J. Sprogis

IPC: H01L2310

CPC classification number: H01L23/4334 ,  H01L23/3677 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/05599 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06568 ,  H01L2225/06582 ,  H01L2225/06586 ,  H01L2225/06589 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18301 ,  H01L2924/19041 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

Abstract: An apparatus for simultaneously removing heat from two surfaces of a semiconductor structure includes a heat sink mounted to a front surface and a heat sink mounted to a back surface of the semiconductor structure. The structure can be two chips mounted in face-to-face arrangement, and the heat sinks remove heat from back surfaces of both chips.

Abstract translation: 同时从半导体结构的两个表面去除热量的装置包括安装到前表面的散热器和安装到半导体结构的后表面的散热片。 该结构可以是以面对面布置安装的两个芯片，并且散热器从两个芯片的背面去除热量。

公开(公告)号：US20130307656A1

公开(公告)日：2013-11-21

申请号：US13474239

申请日：2012-05-17

Applicant: Gary D. Carpenter ,  Alan J. Drake ,  Rachel Gordin ,  Michael J. Shapiro ,  Edmund J. Sprogis

Inventor： Gary D. Carpenter ,  Alan J. Drake ,  Rachel Gordin ,  Michael J. Shapiro ,  Edmund J. Sprogis

IPC: H01F27/40 ,  H01F7/06 ,  H01F27/28

CPC classification number: H01L23/5227 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49827 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/0557 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/15311 ,  H01L2924/30107 ,  Y10T29/49071 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A distributed active transformer is provided comprising a primary and a secondary winding. The primary winding comprises a first set of conductive vias extending in a direction between a first surface and a second surface of an element, a first set of first electrically conductive lines extending along the first surface, and a first set of second electrically conductive lines extending along the second surface. The secondary winding comprises a second set of conductive vias extending in a direction between the first surface and the second surface, a second set of first electrically conductive lines extending along the first surface, and a second set of second electrically conductive lines extending along the second surface. When energized, the primary winding generates magnetic flux extending in a direction parallel to the first surface and the second surface. The secondary winding receives energy transferred by the magnetic flux generated by the primary winding.

Abstract translation: 提供一种分布式有源变压器，其包括初级和次级绕组。 初级绕组包括在元件的第一表面和第二表面之间的方向上延伸的第一组导电通孔，沿着第一表面延伸的第一组第一导电线，以及延伸的第一组第二导电线 沿着第二个表面。 次级绕组包括在第一表面和第二表面之间的方向上延伸的第二组导电通孔，沿着第一表面延伸的第二组第一导电线，以及沿着第二表面延伸的第二组第二导电线 表面。 当通电时，初级绕组产生沿平行于第一表面和第二表面的方向延伸的磁通量。 次级绕组接收由初级绕组产生的磁通传递的能量。

公开(公告)号：US08492816B2

公开(公告)日：2013-07-23

申请号：US12685156

申请日：2010-01-11

Applicant: James S. Nakos ,  Edmund J. Sprogis ,  Anthony K. Stamper

Inventor： James S. Nakos ,  Edmund J. Sprogis ,  Anthony K. Stamper

IPC: H01L27/108 ,  H01L29/94

CPC classification number: H01L28/40 ,  H01L29/66181 ,  H01L29/945

Abstract: Solutions for forming a silicided deep trench decoupling capacitor are disclosed. In one aspect, a semiconductor structure includes a trench capacitor within a silicon substrate, the trench capacitor including: an outer trench extending into the silicon substrate; a dielectric liner layer in contact with the outer trench; a doped polysilicon layer over the dielectric liner layer, the doped polysilicon layer forming an inner trench within the outer trench; and a silicide layer over a portion of the doped polysilicon layer, the silicide layer separating at least a portion of the contact from at least a portion of the doped polysilicon layer; and a contact having a lower surface abutting the trench capacitor, a portion of the lower surface not abutting the silicide layer.

Abstract translation: 公开了用于形成硅化深沟槽去耦电容器的解决方案。 一方面，半导体结构在硅衬底内包括沟槽电容器，所述沟槽电容器包括：延伸到硅衬底中的外沟槽; 介电衬垫层，与所述外沟槽接触; 所述掺杂多晶硅层在所述外部沟槽内形成内部沟槽; 以及在所述掺杂多晶硅层的一部分上的硅化物层，所述硅化物层将所述接触的至少一部分与所述掺杂多晶硅层的至少一部分分离; 以及具有与所述沟槽电容器邻接的下表面的接触件，所述下表面的一部分不邻接所述硅化物层。

公开(公告)号：US20120181700A1

公开(公告)日：2012-07-19

申请号：US13005883

申请日：2011-01-13

Applicant: Jeffrey P. Bonn ,  Brent A. Goplen ,  Brian L. Kinsman ,  Robert M. Rassel ,  Edmund J. Sprogis ,  Daniel S. Vanslette

Inventor： Jeffrey P. Bonn ,  Brent A. Goplen ,  Brian L. Kinsman ,  Robert M. Rassel ,  Edmund J. Sprogis ,  Daniel S. Vanslette

IPC: H01L23/48 ,  G06F17/50

CPC classification number: H01L21/76898 ,  G06F17/5068 ,  G06F2217/80 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embodiments of the invention provide an integrated circuit (IC) having reduced through silicon via (TSV)-induced stresses and related IC design structures and methods. In one embodiment, the invention includes a method of designing an integrated circuit (IC) having reduced substrate stress, the method including: placing in an IC design file a plurality of through silicon via (TSV) placeholder cells, each placeholder cell having an undefined TSV orientation; replacing a first portion of the plurality of TSV placeholder cells with a first group of TSV cells having a first orientation; and replacing a second portion of the plurality of TSV placeholder cells with a second group of TSV cells having a second orientation substantially perpendicular to the first orientation, wherein TSV cells having the first orientation and TSV cells having the second orientation are interspersed to reduce a TSV-induced stress in an IC substrate.

Abstract translation: 本发明的实施例提供了具有减少的通过硅通孔（TSV）的应力和相关IC设计结构和方法的集成电路（IC）。 在一个实施例中，本发明包括设计具有降低的衬底应力的集成电路（IC）的方法，所述方法包括：在IC设计文件中放置多个通过硅通孔（TSV）占位符单元，每个占位符单元具有未定义的 TSV方向 用具有第一取向的第一组TSV单元替换所述多个TSV占位符单元的第一部分; 以及用具有基本上垂直于第一取向的第二取向的第二组TSV单元替换多个TSV占位符单元的第二部分，其中具有第一取向的TSV单元和具有第二取向的TSV单元分散以减少TSV 在IC衬底中引起的应力。