知搜-全球专利检索

  1. Login
  2. Sign Up

Search Results

5706 records (took 0.03 seconds)

    Data processing method and device, decoder, network device and storage medium
    31.
    发明授权
    Data processing method and device, decoder, network device and storage medium 有权

    公开(公告)号：US12113546B2

    公开(公告)日：2024-10-08

    申请号：US18021037

    申请日：2021-08-04

    Applicant: SANECHIPS TECHNOLOGY CO., LTD

    Inventor： Qing Bian

    IPC: H03M13/11

    CPC classification number: H03M13/1125 ,  H03M13/1151

    Abstract: A data processing method for use in a data processing device, a decoder, a network device and/or a computer-readable storage medium. The data processing method includes: classifying log likelihood ratio (LLR) elements according to a modulation mode, a preset decoder quantization threshold and a signal-to-noise ratio, to obtain a classification result; extracting feature information of each category in the classification result; calculating to obtain a scale factor according to the feature information of each category; and scaling the LLR elements according to the scale factor.

    Out-of-order bit-flipping decoders for non-volatile memory devices
    32.
    发明授权
    Out-of-order bit-flipping decoders for non-volatile memory devices 有权

    公开(公告)号：US12112041B2

    公开(公告)日：2024-10-08

    申请号：US17950528

    申请日：2022-09-22

    Applicant: SK hynix Inc.

    Inventor： Fan Zhang ,  Meysam Asadi ,  Haobo Wang

    IPC: G06F3/06 ,  H03M13/11

    CPC classification number: G06F3/0611 ,  G06F3/0659 ,  G06F3/0679 ,  H03M13/1108 ,  H03M13/1111 ,  H03M13/1128

    Abstract: Devices, systems, and methods for reducing a latency of a decoder in a non-volatile memory are described. An example method includes receiving a noisy codeword that is based on a transmitted codeword generated from a low-density parity-check (LDPC) code, the LDPC code having an associated parity matrix comprising a plurality of columns of circulant matrices, performing a sorting operation that sorts the plurality of columns of circulant matrices in a descending order of a first quality metric to generate a plurality of sorted columns of circulant matrices, the first quality metric indicative of a number of errors in a corresponding column of circulant matrices, and iteratively processing the plurality of sorted columns of circulant matrices to determine a candidate version of the transmitted codeword.

    Data error correction method, apparatus, device, and readable storage medium
    33.
    发明授权
    Data error correction method, apparatus, device, and readable storage medium 有权

    公开(公告)号：US12107601B2

    公开(公告)日：2024-10-01

    申请号：US17733165

    申请日：2022-04-29

    Applicant: SHENZHEN DAPU MICROELECTRONICS CO., LTD.

    Inventor： Yan Wang ,  Weijun Li

    IPC: H03M13/00 ,  G06N3/08 ,  H03M13/03 ,  H03M13/11

    CPC classification number: H03M13/033 ,  G06N3/08 ,  H03M13/1102

    Abstract: A data error correction method, apparatus, device, and readable storage medium are disclosed. The method includes: acquiring target data to be error-corrected; performing error correction on the target data using an error-correcting code to obtain first data; judging whether the performing of the error correction on the target data is successful; responsive to the performing of the error correction on the target data being not successful, correcting the target data using a target neural network to obtain second data, determining the second data as the target data, and continuing to perform the error correction on the target data again; and responsive to the performing of the error correction on the target data being successful, determining the first data as the error-corrected target data.

    Registration of a PUF signature and regeneration using a trellis decoder
    37.
    发明授权
    Registration of a PUF signature and regeneration using a trellis decoder 有权

    公开(公告)号：US12081238B2

    公开(公告)日：2024-09-03

    申请号：US18084974

    申请日：2022-12-20

    Applicant: Xilinx, Inc.

    Inventor： James Wesselkamper

    IPC: H03M13/25 ,  H03M13/11

    CPC classification number: H03M13/256 ,  H03M13/1111

    Abstract: A physically unclonable function includes a circuit that translates a normally distributed sequence of raw sample into a sequence of uniformly distributed binned values across sub-bins of bins. Helper circuitry generates centering values and parity bits based on binned values generated during registration. Each centering value is associated with a raw sample value corresponding to a binned value and indicates an offset of a sub-bin in one of the bins. A distance calculator generates a set of distances from each raw sample value based on the centering value associated with the raw sample value. Each distance indicates a difference between the respective raw sample value and a raw sample value equivalent to a midpoint of a sub-bin offset by the associated centering value in a bin. A trellis decoder generates a PUF signature based on the candidate symbols, sets of distances, and parity bits.

    Syndrome check functionality to differentiate between error types
    38.
    发明授权
    Syndrome check functionality to differentiate between error types 有权

    公开(公告)号：US12081235B2

    公开(公告)日：2024-09-03

    申请号：US18098995

    申请日：2023-01-19

    Applicant: Micron Technology, Inc.

    Inventor： Scott E. Schaefer

    IPC: H03M13/11 ,  H03M13/00 ,  H03M13/43

    CPC classification number: H03M13/1111 ,  H03M13/43 ,  H03M13/611

    Abstract: Methods, systems, and devices for syndrome check functionality to differentiate between error types are described. A host system, a memory system, or some combination of both may include syndrome check circuitry to provide enhanced error diagnostic capabilities for data communicated between the host system and the memory system. The syndrome check circuitry may receive a first signal from the memory system indicating whether the memory system detected and attempted to correct an error in the data and may receive a second signal from the host system indicating whether the host system detected an error in the received data. The syndrome check circuitry may compare the first signal and the second signal using a set of logic gates to differentiate between different combinations of errors detected at one or both of the memory system or the host system.

Patent Agency Ranking