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公开(公告)号：US20240394181A1
公开(公告)日：2024-11-28
申请号：US18795962
申请日：2024-08-06
Applicant: KIOXIA CORPORATION
Inventor： Shinichi KANNO
IPC: G06F12/02 , G06F12/1009 , G06F13/16 , G11C16/08 , G11C16/26
Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller. In response to receiving a first write command from a host, the controller determines a first physical address indicative of a physical storage location of the nonvolatile memory to which first write data associated with the first write command is to be written, and updates an address translation table such that the first physical address is associated with a logical address of the first write data. The controller starts updating the address translation table before the transfer of the first write data is finished or before the write of the first write data to the nonvolatile memory is finished.
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公开(公告)号：US12154635B2
公开(公告)日：2024-11-26
申请号：US17410265
申请日：2021-08-24
Applicant: SanDisk Technologies LLC
Inventor： Yu-Chung Lien , Henry Chin , Erika Penzo
Abstract: A memory device that includes a plurality of memory cells arranged in an array is provided. A control circuitry is configured to program a single bit of data in each memory cell of the plurality of memory cells. The control circuitry is further configured to program a first set of memory cells of the plurality of memory cells using a first programming operation that includes a single programming pulse and no verify pulse and program a second set of memory cells of the plurality of memory cells using a second programming operation that includes at least one programming loop with a programming pulse and a verify pulse.
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公开(公告)号：US12153804B1
公开(公告)日：2024-11-26
申请号：US18224845
申请日：2023-07-21
Applicant: Western Digital Technologies, Inc.
Inventor： Nitin Jain , Maharudra Nagnath Swami
Abstract: Some areas (e.g., boundary wordlines) in a block of memory can be more error prone than others. Typically, errors in these areas are not detected until after the entire block is programmed. Handling such errors then can result in performance penalties and large data relocations. With the embodiments presented herein, a two-stage programming operation is provided. In the first stage, only the error-prone areas of the block are programmed, and a check is made to determine if an error occurred in that programming. In the second stage, the remaining portions of the block are programmed, but that only occurs after it is determined that the error-prone areas have been programmed successfully. Detecting and dealing with errors in the error-prone areas before the entire block is programmed avoid the performance penalties and large data relocations noted above.
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公开(公告)号：US20240386930A1
公开(公告)日：2024-11-21
申请号：US18229019
申请日：2023-08-01
Applicant: Western Digital Technologies, Inc.
Inventor： Mohan Vamsi Dunga , Xiang Yang , Keyur Payak
Abstract: A memory device is provided and includes a memory block that has a plurality of memory cells that are arranged in a plurality of word lines. The memory device also includes a plurality of word line switch transistors that are electrically coupled with the plurality of word lines. Some of the word line switch transistors have a first width and some of the word line switch transistors have a second width that is different than the first width. By providing the word line switch transistors with different widths, the size of a word line switch area in the memory device can be optimized.
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公开(公告)号：US20240386918A1
公开(公告)日：2024-11-21
申请号：US18457351
申请日：2023-08-29
Applicant: SK hynix Inc.
Inventor： Nam Jae LEE
Abstract: A semiconductor device may include: a first gate structure including first gate lines, a first step structure including first pads, a first gap-fill insulating layer located between the first gate lines and the first step structure, and first wiring lines connecting the first gate lines and the first pads, respectively; and a second gate structure including second gate lines located on the first gate lines, a second step structure located on the first gap-fill insulating layer and including second pads, a second gap-fill insulating layer located on the first step structure, and second wiring lines connecting the second gate lines and the second pads, respectively.
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Patent Agency Ranking
公开(公告)号：US20240379165A1
公开(公告)日：2024-11-14
申请号：US18781505
申请日：2024-07-23
Applicant: SK hynix Inc.
Inventor： Jae Woong KIM
Abstract: A memory device including a plurality of memory cells, a peripheral circuit configured to perform a read operation of reading data from memory cells connected to a selected word line, and a read operation controller configured to apply a plurality of read voltages to the selected word line, apply a first pass voltage to unselected word lines while first read voltages for determining a program state of memory cells having a threshold voltage higher than a reference voltage among the plurality of read voltages are applied to the selected word line, and apply a second pass voltage higher than the first pass voltage to the unselected word line while second read voltages for determining a program state of memory cells having a threshold voltage lower than the reference voltage among the plurality of read voltages are applied to the selected word line.
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公开(公告)号：US12136458B2
公开(公告)日：2024-11-05
申请号：US17897089
申请日：2022-08-26
Applicant: KIOXIA CORPORATION
Inventor： Tomoki Nakagawa , Koji Kato , Shuhei Oketa , Mai Shimizu
Abstract: A semiconductor memory device includes a memory string, a voltage supply circuit, a plurality of control signal lines, a row decoder, and a control circuit. The voltage supply circuit is configured to generate a plurality of operation voltages to operate the semiconductor memory device. The operation voltages include a negative voltage. The plurality of control signal lines is connected between the voltage supply circuit and the memory string. The row decoder includes a plurality of transistors provided in the plurality of control signal lines, respectively. The control circuit is configured to control the transistors of the row decoder, and cause the negative voltage to be supplied to the row decoder during a certain period of time in which a voltage of one of the control signal lines drops to a negative level.
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公开(公告)号：US20240363173A1
公开(公告)日：2024-10-31
申请号：US18768091
申请日：2024-07-10
Applicant: Intel NDTM US LLC
Inventor： Narayanan RAMANAN
CPC classification number: G11C16/26 , G11C16/0483 , G11C16/08 , G11C16/30 , G11C16/3427
Abstract: Modulation of the source voltage in a NAND-flash array read waveform can enable improved read-disturb mitigation. For example, increasing the source line voltage to a voltage with a magnitude greater than the non-idle source voltage during the read operation when the array is idle (e.g., not during sensing) enables a reduction in read disturb without the complexity arising from the consideration of multiple read types. Additional improvement in FN disturb may also be obtained on the sub-blocks in the selected SGS by increasing the source line voltage during the selected wordline ramp when the array is idle.
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公开(公告)号：US20240363168A1
公开(公告)日：2024-10-31
申请号：US18230336
申请日：2023-08-04
Applicant: Western Digital Technologies, Inc.
Inventor： Abhijith Prakash , Xiang Yang
CPC classification number: G11C16/14 , G11C16/0483 , G11C16/08 , G11C16/24 , G11C16/30 , H10B41/27 , H10B41/35 , H10B43/27 , H10B43/35
Abstract: The memory device includes a chip with at least one voltage pump and a plurality of planes. The planes have arrays of memory cells that can be programmed and erased. At least some of the planes are at different distances from the at least one voltage pump. The memory device further includes control circuitry that is configured to program and erase the memory cells. The control circuitry is further configured to supply at least one voltage to a selected plane of the plurality of planes during a programming operation or an erase pulse and adjust the at least one voltage that is supplied to the selected plane by a parameter that is determined based on a distance between the selected plane and the at least one voltage pump.
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公开(公告)号：US12131789B2
公开(公告)日：2024-10-29
申请号：US17847545
申请日：2022-06-23
Applicant: Samsung Electronics Co., Ltd.
Inventor： Junho Kim , Jinyoung Kim , Sehwan Park , Seoyoung Lee , Jisang Lee , Joonsuc Jang
CPC classification number: G11C16/3459 , G11C16/08 , G11C16/102 , G11C16/26 , G11C16/3404
Abstract: Aggressor memory cells connected to one or more aggressor wordlines are grouped into aggressor cell groups by performing a read operation with respect to the aggressor wordlines based on one or more grouping read voltages, where the aggressor wordlines are adjacent to a selected wordline corresponding to a read address among wordlines of a memory block. Selected memory cells connected to the selected wordline are grouped into a selected cell groups respectively corresponding to the aggressor cell groups. Group read conditions respectively corresponding to the selected cell groups are determined and group read operations are performed with respect to the plurality of selected cell groups based on the group read conditions. The read errors are reduced by grouping the selected memory cells into the selected cell groups according to the change of operation environments.
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