公开(公告)号：US20240363173A1

公开(公告)日：2024-10-31

申请号：US18768091

申请日：2024-07-10

Applicant: Intel NDTM US LLC

Inventor： Narayanan RAMANAN

IPC: G11C16/26 ,  G11C16/04 ,  G11C16/08 ,  G11C16/30 ,  G11C16/34

CPC classification number: G11C16/26 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/30 ,  G11C16/3427

Abstract: Modulation of the source voltage in a NAND-flash array read waveform can enable improved read-disturb mitigation. For example, increasing the source line voltage to a voltage with a magnitude greater than the non-idle source voltage during the read operation when the array is idle (e.g., not during sensing) enables a reduction in read disturb without the complexity arising from the consideration of multiple read types. Additional improvement in FN disturb may also be obtained on the sub-blocks in the selected SGS by increasing the source line voltage during the selected wordline ramp when the array is idle.