公开(公告)号：US20120043254A1

公开(公告)日：2012-02-23

申请号：US13266029

申请日：2009-05-13

申请人： Kazuya Inoue

发明人： Kazuya Inoue

IPC分类号： B65D85/86

CPC分类号： H01L21/67366 ,  H01L21/67386

摘要： Wafer protecting grooves (10) are provided on an innermost wall (1b) of a container body (1). The wafer protecting grooves have a cross-sectional configuration in the shape of undulations having bottoms (10b), which are most distant from an opening (1a), at respective positions facing the outer edges of semiconductor wafers (W), and having an opening width wider than the thickness of each semiconductor wafer (W). In a normal state, an imaginary line (Q) connecting together the tops of the undulations is inward of or at the same position as the outer edges of the semiconductor wafers (W) facing the imaginary line. Thus, it is possible to obtain superior impact resistance that makes the semiconductor wafers (W) in the container body (1) unlikely to be damaged even when a large impact is applied thereto by a fall or other handling errors.

摘要翻译： 在容器主体（1）的最内壁（1b）上设置有晶片保护槽（10）。 晶片保护槽具有在与半导体晶片（W）的外边缘相对的各个位置上具有与开口（1a）最远的底部（10b）的波状形状的横截面构造，并且具有开口 宽度大于每个半导体晶片（W）的厚度。 在正常状态下，将波纹顶部连接在一起的假想线（Q）位于与假想线对置的半导体晶片（W）的外边缘的内侧或与其相同的位置。 因此，即使通过跌倒或其他处理误差对其施加大的冲击，也可以获得使容器主体（1）中的半导体晶片（W）不会受到损坏的优异的抗冲击性。

公开(公告)号：US20100294781A1

公开(公告)日：2010-11-25

申请号：US12597031

申请日：2008-04-23

申请人： Kazuyoshi Kaneko ,  Priscille Angot

发明人： Kazuyoshi Kaneko ,  Priscille Angot

IPC分类号： B65D6/00 ,  C08L45/00 ,  C08K5/06 ,  C08K5/17 ,  C08K5/20 ,  C08K5/1535 ,  C08K5/11 ,  C08K5/42 ,  C08K5/52 ,  C08K5/53 ,  C08K5/5333

CPC分类号： C08L23/20 ,  C08L9/06 ,  C08L23/00 ,  C08L23/02 ,  C08L65/00 ,  H01L21/67366 ,  C08L2666/06 ,  C08L2666/04

摘要： A resin composition of the present invention contains 99 to 30 parts by weight of a cyclic olefin polymer (A); 1 to 70 parts by weight of a soft copolymer (B) obtained by polymerizing at least two kinds of monomers selected from the group consisting of olefins, dienes, and aromatic vinyl hydrocarbons and having a glass transition temperature of 0° C. or lower; and relative to 100 parts by weight of total amount of the cyclic olefin polymer (A) and the soft copolymer (B), 0.001 to 1 part by weight of a radical initiator (C), 0 to 1 part by weight of a polyfunctional compound (D) having two or more radically polymerizable functional groups in a molecule, and 0.5 to 10 parts by weight of a nonionic or anionic antistatic agent (E).

摘要翻译： 本发明的树脂组合物含有99〜30重量份的环烯烃聚合物（A）; 1〜70重量份通过使选自烯烃，二烯和芳族乙烯基烃中的至少2种单体聚合并且玻璃化转变温度为0℃以下的软质共聚物（B） 相对于100重量份的环烯烃聚合物（A）和软共聚物（B）的总量，0.001〜1重量份的自由基引发剂（C），0〜1重量份的多官能化合物 （D）在分子中具有两个以上自由基聚合性官能团，0.5〜10重量份的非离子或阴离子抗静电剂（E）。

公开(公告)号：US20100236976A1

公开(公告)日：2010-09-23

申请号：US12548368

申请日：2009-08-26

申请人： JAMES D. PYLANT ,  ALAN L. WABER

发明人： JAMES D. PYLANT ,  ALAN L. WABER

IPC分类号： B65D85/30

CPC分类号： H01L21/67386 ,  H01L21/67353 ,  H01L21/67366 ,  H01L21/67369 ,  H01L21/67373 ,  H01L21/67379

摘要： Improvements in a semiconductor wafer container including improvements in side protection to the wafers, improved cover design to minimize rotation, a simplified top cover orientation mechanism and an improved bottom holding mechanism for automation. The side protection to the wafers is with multiple staggered inner and outer walls. The improved cover design improves alignment of the top and bottom housings and minimizes rotation of the housings in transit or motion. The housings have a recessed tab ramp feature with bi-directional locking that also increases the rigidity of the containment device when the two housings are assembled. The improved bottom holding mechanism for automation is an integrated feature that is molded into the bottom housing and not assembled in a secondary operation. The molded integration reduces tolerance errors that are present in assembling multiple pieces and joining multiple pieces.

摘要翻译： 半导体晶片容器的改进，包括对晶片的侧面保护的改进，改进的盖设计以使旋转最小化，简化的顶盖定向机构和用于自动化的改进的底部保持机构。 对晶片的侧面保护是具有多个交错的内壁和外壁。 改进的盖设计改善了顶部和底部壳体的对准，并最大限度地减少了运输或运动中壳体的旋转。 这些外壳具有带双向锁定的凹陷突出部斜面特征，当两个壳体组装时，这也增加了容纳装置的刚度。 用于自动化的改进的底部保持机构是模制到底部壳体中并且未组装在二次操作中的集成特征。 模制集成减少了组装多个零件并连接多个零件时出现的公差错误。

公开(公告)号：US07784178B2

公开(公告)日：2010-08-31

申请号：US11771654

申请日：2007-06-29

申请人： Peter Davison

发明人： Peter Davison

IPC分类号： H01K3/22

CPC分类号： H01L21/67366 ,  B29C45/0001 ,  B29C45/0005 ,  B29K2105/0079 ,  B29K2307/00 ,  H01L21/67379 ,  Y10T29/49158 ,  Y10T29/49172 ,  Y10T29/4922

摘要： Techniques associated with higher performance barrier materials for containers to contain one or more environmentally sensitive devices associated with semiconductor manufacture are generally described. In one example, an apparatus includes an enclosure to contain one or more environmentally sensitive devices associated with semiconductor manufacture, the enclosure comprising a liquid crystal polymer (LCP) to provide a barrier against at least water and oxygen and to reduce purging requirements, and a door coupled with the enclosure.

摘要翻译： 通常描述与用于容器的用于容纳与半导体制造相关联的一个或多个环境敏感设备的高性能阻隔材料相关联的技术。 在一个示例中，设备包括外壳以容纳与半导体制造相关联的一个或多个环境敏感设备，所述外壳包括液晶聚合物（LCP），以提供至少防止水和氧的屏障并降低清洗要求，以及 门与外壳相连。

公开(公告)号：US20090200250A1

公开(公告)日：2009-08-13

申请号：US12012984

申请日：2008-02-07

申请人： Boris Kesil

发明人： Boris Kesil

IPC分类号： H01L21/673

CPC分类号： H01L21/67373 ,  H01L21/67366

摘要： A wafer container made from a polymer material with inner walls of the container coated with a thin easily washable wear-resistant and scratch-resistant barrier layer of SiO2 for preventing penetration of products of diffusion of polymers, such as free radicals, into the interior space of the carrier that retains a wafer. The SiO2 coatings on the walls of the container are applied by the PECVD process. The wafer container of the invention can be manufactured at low cost by molding it from a less expensive and lower grade polymer.

摘要翻译： 由聚合物材料制成的晶片容器，其容器的内壁涂有薄的易于洗涤的耐磨和耐刮擦的SiO 2阻挡层，用于防止聚合物如自由基扩散产物渗入内部空间 的保持晶片的载体。 通过PECVD工艺施加容器壁上的SiO 2涂层。 本发明的晶片容器可以通过从较便宜和较低级别的聚合物成型而以低成本制造。

公开(公告)号：US20080217291A1

公开(公告)日：2008-09-11

申请号：US12028904

申请日：2008-02-11

申请人： Masakazu HIGUMA ,  Yasuharu Sasaki ,  Tadashi Aoto ,  Eiichiro Kikuchi

发明人： Masakazu HIGUMA ,  Yasuharu Sasaki ,  Tadashi Aoto ,  Eiichiro Kikuchi

IPC分类号： C23F1/00 ,  B44C1/22

CPC分类号： H01L21/68757 ,  C23C16/4581 ,  H01J37/20 ,  H01L21/67366 ,  H01L21/6875

摘要： A substrate mounting stage that prevents poor attraction of substrates so as to improve the operating rate of a substrate processing apparatus. The substrate mounting stage is disposed in the substrate processing apparatus and has a substrate mounting surface on which a substrate is mounted. The arithmetic average roughness (Ra) of the substrate mounting surface is not less than a first predetermined value, and the initial wear height (Rpk) of the substrate mounting surface is not more than a second predetermined value.

摘要翻译： 一种基板安装台，其防止基板的吸引力降低，从而提高基板处理装置的运转速度。 基板安装台设置在基板处理装置中，并且具有安装有基板的基板安装面。 基板安装面的算术平均粗糙度（Ra）不小于第一预定值，并且基板安装表面的初始磨损高度（Rpk）不大于第二预定值。

公开(公告)号：US07168564B2

公开(公告)日：2007-01-30

申请号：US11092528

申请日：2005-03-29

申请人： Sanjiv M. Bhatt ,  Shawn D. Eggum

发明人： Sanjiv M. Bhatt ,  Shawn D. Eggum

IPC分类号： B65D85/48

CPC分类号： B29C45/0003 ,  B29C45/16 ,  B29K2995/0087 ,  B29L2031/16 ,  G03F7/70691 ,  G03F7/708 ,  H01L21/67313 ,  H01L21/6732 ,  H01L21/67326 ,  H01L21/67366 ,  H01L21/67373 ,  H01L21/67383

摘要： A composite wafer carrier according to an embodiment of the present invention comprises an operative portion formed of a first thermoplastic material and a support portion formed of a second different thermoplastic material. One of the operative portion and support portion is overmolded onto the other to form a gapless hermitic interface that securely bonds the portions together. The operative portion may be a transparent window, a portion of a latching mechanism or a wafer contact portion. Preferred embodiments of the invention include wafer carriers with said features, process carriers with said features and a process for manufacturing wafer carriers with said features.

摘要翻译： 根据本发明实施例的复合晶片载体包括由第一热塑性材料形成的操作部分和由第二不同热塑性材料形成的支撑部分。 其中一个操作部分和支撑部分被包覆模制在另一个上，以形成将这些部分牢固地结合在一起的无间隙的密封界面。 操作部分可以是透明窗口，闩锁机构的一部分或晶片接触部分。 本发明的优选实施例包括具有所述特征的晶片载体，具有所述特征的工艺载体和用于制造具有所述特征的晶片载体的工艺。

公开(公告)号：US07059475B2

公开(公告)日：2006-06-13

申请号：US09971352

申请日：2001-10-04

申请人： Michael C. Zabka ,  Matthew Nicolas ,  David Molitor

发明人： Michael C. Zabka ,  Matthew Nicolas ,  David Molitor

IPC分类号： B65D85/30

CPC分类号： H01L21/67366 ,  H01L21/67369 ,  H01L21/67386

摘要： The invention relates to transport and shipping containers for wafers that are processed into semiconductor units. The wafer transport system provides wafer carriers that provide damage protection and particulate protection with minimal contamination of the wafers in the shipper. The invention includes a wafer cushion for cushioning semiconductor wafers that is made of a closed-cell polyethylene material with a surface resistivity of less than 5×107 ohms per square that has less than 1800 ng/g Cl−, 400 ng/g F−/Acetate, 270 ng/g NO3−, 350 ng/g SO42−, and 60 ng/g PO43−ions leachable under moderate conditions. The wafer cushion optimally has no detectable outgassing organics under stringent conditions. The static control properties are the result of carbon that is part of the structure of the material.

摘要翻译： 本发明涉及用于加工成半导体单元的晶片的运输和运输容器。 晶片输送系统提供晶片载体，其提供损伤保护和颗粒保护，同时托运人中晶片的污染最小。 本发明包括用于缓冲半导体晶片的晶片衬垫，其由表面电阻率小于每平方米5×10 7欧姆的闭孔聚乙烯材料制成，其具有小于1800ng / g的Cl

公开(公告)号：US20040187451A1

公开(公告)日：2004-09-30

申请号：US10766565

申请日：2004-01-29

发明人： Yoko Suzuki ,  Akira Tanaka ,  Takashi Kishi

IPC分类号： B01D050/00

CPC分类号： H01L21/67366 ,  H01L21/67017 ,  H01L21/67379 ,  H01L21/67393 ,  H01L21/67396 ,  H01L21/67772 ,  H01L21/67775

摘要： A method of using a substrate transport pod is suitable for manufacturing semiconductor devices with copper wiring and low dielectric insulating film having dielectric constants of less than 3. The method is based on loading the substrates into a pod from an atmosphere of a first process, and circulating a gaseous atmosphere through interior of the pod in such a way to selectively remove at least one contaminant including moisture, particulate substances or chemical substances, and to expose the substrates to a controlled atmosphere intermittently or continually while the substrates are held in the pod before they are unloaded from the pod and introduced into a second process. For a pod that is used to house the substrates for the purpose of retaining or transporting, the pod has a pod main body and a door that provides a hermetic seal, the pod is made primarily of a materiel that has moisture absorption factor of less than 0.1 %, the pod can contact the substrates directly or indirectly and has a conductive area so as to enable static charges to be guided out of the pod.

摘要翻译： 使用衬底传输盒的方法适用于制造具有铜布线的半导体器件和具有小于3的介电常数的低介电绝缘膜。该方法是基于将第一工艺的气氛将衬底加载到容器中，以及 循环气体气氛通过荚的内部，以选择性地去除包括水分，颗粒物质或化学物质在内的至少一种污染物，并将基片间断地或连续地暴露于受控气氛，同时将基底保持在荚内 它们从pod中卸载并引入第二个进程。 对于用于容纳用于保持或运输的基材的荚，荚具有荚主体和提供气密密封的门，所述荚主要由具有小于等于的吸湿因子的材料制成 0.1％，荚可以直接或间接接触基板，并具有导电区域，以使静电荷能够被引导出荚。

公开(公告)号：US06715495B2

公开(公告)日：2004-04-06

申请号：US09737125

申请日：2000-12-13

申请人： Giang T. Dao ,  Ronald J. Kuse

发明人： Giang T. Dao ,  Ronald J. Kuse

IPC分类号： B08B704

CPC分类号： H01L21/67359 ,  G03F1/62 ,  G03F1/66 ,  G03F7/70741 ,  G03F7/70916 ,  G03F7/70925 ,  G03F7/70983 ,  H01L21/67366 ,  H01L21/67393

摘要： A method of transporting a reticle is disclosed. The reticle is placed in a reticle carrier that has an ionizer. Moreover, the reticle may be attached with a pellicle. The pellicle consists of a pellicle frame and a pellicle film stretched over the pellicle frame. The pellicle frame has included within an absorbent material.

摘要翻译： 公开了传送掩模版的方法。 将掩模版放置在具有电离器的掩模版载体中。 此外，掩模版可以附着防护薄膜组件。 防护薄膜组件由防护薄膜组件框架和在防护薄膜框架上延伸的防护薄膜组成。 防护薄膜框架包括在吸收材料内。