公开(公告)号：US08842470B1

公开(公告)日：2014-09-23

申请号：US13479909

申请日：2012-05-24

Applicant: Xueshi Yang ,  Zining Wu

Inventor： Xueshi Yang ,  Zining Wu

IPC: G11C16/04

CPC classification number: G11C16/26 ,  G11C11/5642 ,  G11C16/3436

Abstract: A memory control module includes a read module configured to receive a first signal read from a first storage region of a memory cell, and receive a second signal read from a second storage region of the memory cell. A data detection module is configured to, based on a noiseless signal, detect respective data in each of the first storage region and the second storage region. The noiseless signal includes an ideal signal and an interference signal associated with at least one of the first signal and the second signal.

Abstract translation: 存储器控制模块包括读取模块，其被配置为接收从存储器单元的第一存储区域读取的第一信号，并且接收从存储器单元的第二存储区域读取的第二信号。 数据检测模块被配置为基于无噪声信号来检测第一存储区域和第二存储区域中的每一个中的相应数据。 无噪声信号包括与第一信号和第二信号中的至少一个相关联的理想信号和干扰信号。

公开(公告)号：US20140177342A1

公开(公告)日：2014-06-26

申请号：US14132124

申请日：2013-12-18

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Violante Moschiano ,  Domenico Di Cicco ,  Andrea D'Alessandro

IPC: G11C16/26

CPC classification number: G11C16/26 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/3436

Abstract: The present disclosure includes devices, methods, and systems including memory cell sensing using a boost voltage. One or more embodiments include pre-charging and/or floating a data line associated with a selected memory cell, boosting the pre-charged and/or floating data line, and determining a state of the selected memory cell based on a sensed discharge of the data line after boosting the data line.

Abstract translation: 本公开包括包括使用升压电压的存储器单元感测的装置，方法和系统。 一个或多个实施例包括预先充电和/或浮动与所选择的存储器单元相关联的数据线，升压预充电和/或浮置数据线，以及基于感测到的放电，确定所选择的存储器单元的状态 提升数据线后的数据线。

公开(公告)号：US08737129B2

公开(公告)日：2014-05-27

申请号：US13355834

申请日：2012-01-23

Applicant: Changhyun Lee ,  Jungdal Choi ,  Byeong-In Choe

Inventor： Changhyun Lee ,  Jungdal Choi ,  Byeong-In Choe

IPC: G11C16/10 ,  G11C16/26 ,  G11C16/34 ,  G11C11/56

CPC classification number: G11C16/26 ,  G11C8/10 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3418 ,  G11C16/3436 ,  G11C16/3454 ,  G11C16/3459 ,  G11C29/00

Abstract: A nonvolatile memory device has improved reliability by compensating a threshold voltage of a flash memory cell. A nonvolatile memory device includes a memory cell array and a voltage generator for supplying a select read voltage to a select word line and an unselect read voltage to unselected word lines when a read operation is performed, and supplying a verify voltage to a select word line and the unselect read voltage to unselected word lines when a program operation is performed. The voltage generator supplies a first unselect read voltage to at least one between an upper word line and a lower word line adjacent to the select word line when the program operation is performed, and supplies a second unselected read voltage to at least one between the upper word line and the lower word line adjacent to the select word line when the read operation is performed.

Abstract translation: 非易失性存储器件通过补偿闪存单元的阈值电压而提高了可靠性。 非易失性存储器件包括：存储单元阵列和电压发生器，用于在执行读取操作时将选择读取电压提供给选择字线，并将未选择读取电压提供给未选择的字线;以及将验证电压提供给选择字线 以及当执行编程操作时，对未选字线的取消选择读取电压。 电压发生器在执行编程操作时将第一未读选择电压提供给与选择字线相邻的上字线和下字线之间的至少一个，并且将第二未选择读电压提供给上 当执行读操作时，字线和与选择字线相邻的下字线。

公开(公告)号：US08659951B2

公开(公告)日：2014-02-25

申请号：US13423708

申请日：2012-03-19

Applicant: Hidefumi Nawata

Inventor： Hidefumi Nawata

IPC: G11C11/34

CPC classification number: G11C16/10 ,  G11C16/0483 ,  G11C16/3436

Abstract: A bit line is electrically connected to one end of a current path of a memory cell. A word line is commonly connected to the memory cells arranged in a direction intersecting the bit line. A control circuit executes a write operation for applying a write voltage to the word line so shift a threshold voltage of the memory cell to be data written that the threshold voltage of the memory cell to be data written reaches a certain threshold voltage. During the write operation, the control circuit, while applying a gradually rising write voltage to the word line, gradually changes a voltage applied to the bit line based on a relationship between the threshold voltage of the memory cell to be written and a number of times of the write voltage applications.

Abstract translation: 位线电连接到存储器单元的当前路径的一端。 字线通常连接到沿与位线相交的方向排列的存储单元。 控制电路执行用于向字线施加写入电压的写入操作，从而将要写入的数据的存储器单元的阈值电压移位为要写入数据的存储器单元的阈值电压达到一定的阈值电压。 在写入操作期间，控制电路在向字线施加逐渐增加的写入电压的同时，基于要写入的存储器单元的阈值电压与次数之间的关系逐渐改变施加到位线的电压 的写电压应用。

公开(公告)号：US08634253B2

公开(公告)日：2014-01-21

申请号：US13618213

申请日：2012-09-14

Applicant: Frank Chen ,  Zhao Wei ,  Yuan Rong

Inventor： Frank Chen ,  Zhao Wei ,  Yuan Rong

IPC: G11C16/04

CPC classification number: G11C16/10 ,  G11C16/34 ,  G11C16/3436 ,  G11C2207/2245

Abstract: The present disclosure includes methods, devices, modules, and systems for operating semiconductor memory. One method embodiment includes determining a status of a page of memory cells without using input/output (I/O) circuitry, and outputting the status through the I/O circuitry.

Abstract translation: 本公开包括用于操作半导体存储器的方法，设备，模块和系统。 一种方法实施例包括在不使用输入/输出（I / O）电路的情况下确定一页存储器单元的状态，并通过I / O电路输出状态。

公开(公告)号：US20130343132A1

公开(公告)日：2013-12-26

申请号：US14012602

申请日：2013-08-28

Applicant: Micron Technology, Inc.

Inventor： Violante MOSCHIANO ,  Giovanni SANTIN

IPC: G11C16/34 ,  G11C16/24

CPC classification number: G11C16/3436 ,  G11C11/56 ,  G11C11/5628 ,  G11C16/00 ,  G11C16/06 ,  G11C16/10 ,  G11C16/24 ,  G11C16/3454 ,  G11C16/3481 ,  G11C2029/0409

Abstract: Apparatus and methods for determining pass/fail condition of memories are disclosed. In at least one embodiment, a set of common lines, one for each rank of page buffers corresponding to a page, determine the pass/fail status of all connected memory cells, and the pass/fail status results for each line can be combined to determine a pass/fail for the page of memory.

Abstract translation: 公开了用于确定存储器的通过/失败状态的装置和方法。 在至少一个实施例中，对于与页面相对应的每个页面缓冲器等级的一组公共线路确定所有连接的存储器单元的通过/失败状态，并且可以将每行的通过/失败状态结果组合 确定内存页面的通过/失败。

公开(公告)号：US20130254498A1

公开(公告)日：2013-09-26

申请号：US13780774

申请日：2013-02-28

Applicant: SONY CORPORATION

Inventor： Naohiro Adachi ,  Keiichi Tsutsui ,  Kenichi Nakanishi ,  Hideaki Okubo ,  Yasushi Fujinami ,  Ken Ishii

IPC: G06F9/30

CPC classification number: G06F12/0246 ,  G06F9/3004 ,  G06F12/0238 ,  G06F2212/7201 ,  G06F2212/7202 ,  G06F2212/7203 ,  G06F2212/7205 ,  G06F2212/7207 ,  G06F2212/7209 ,  G06F2212/7211 ,  G11C13/0069 ,  G11C13/0097 ,  G11C16/3436 ,  G11C2013/0076

Abstract: A storage control apparatus includes: a pre-processing-execution determining block for determining whether or not either one of an erase operation and a program operation is to be executed as pre-processing in a write operation to be carried out on a predetermined data area to serve as a write-operation object; and a pre-read processing block for reading out pre-read data from the data area prior to the write operation if a result of the determination indicates that the pre-processing is to be executed. The apparatus further includes a bit operating block for carrying out: the pre-processing and one of the erase and program operations which is not the pre-processing as post-processing if a result of the determination indicates that the pre-processing is to be executed; and the post-processing without carrying out the pre-processing if a determination result indicates that the pre-processing is not to be executed.

公开(公告)号：US08520441B2

公开(公告)日：2013-08-27

申请号：US12947693

申请日：2010-11-16

Applicant: Jong Hak Yuh

Inventor： Jong Hak Yuh

IPC: G11C16/06

CPC classification number: G11C16/10 ,  G11C11/5628 ,  G11C16/12 ,  G11C16/3436

Abstract: Methods and devices for sensing non-volatile storage are disclosed. Technology disclosed herein reduces the time for sensing operations of non-volatile storage such as read and program verify. In one embodiment, a kicking voltage is applied to a selected word line during a sensing operation. The kicking voltage may be applied to one end of a selected word line during a transition from a first reference voltage to a second reference voltage. The kicking voltage may help the other end of the word line reach the second reference voltage quickly. Since the bit lines can be sensed after the selected word line has reached the target reference voltage, the time delay prior to sensing of the bit lines may be reduced.

Abstract translation: 公开了用于感测非易失性存储器的方法和装置。 本文公开的技术减少了非易失性存储的感测操作的时间，例如读取和程序验证。 在一个实施例中，在感测操作期间将踢电压施加到所选择的字线。 在从第一参考电压到第二参考电压的转变期间，可以将踢电压施加到所选字线的一端。 踢脚电压可能有助于字线的另一端迅速达到第二个参考电压。 由于可以在所选择的字线达到目标参考电压之后检测位线，所以可以减少感测位线之前的时间延迟。

公开(公告)号：US20130163335A1

公开(公告)日：2013-06-27

申请号：US13601882

申请日：2012-08-31

Applicant: Byung Ryul KIM ,  Duck Ju KIM

Inventor： Byung Ryul KIM ,  Duck Ju KIM

IPC: G11C16/04

CPC classification number: G11C16/10 ,  G11C16/0483 ,  G11C16/06 ,  G11C16/3436

Abstract: A semiconductor memory device is operated by, inter alia, sequentially inputting program data to page buffers coupled to selected pages of at least four planes in order to program selected memory cells included in the selected pages; performing a program operation on each of the four planes; performing a program verify operation on each of the four planes; and inputting new program data for next pages to the page buffers coupled to the next pages, after determining the selected pages of at least two of the four planes have passed the program verify operation, while performing the program operations and the program verify operations on the two remaining planes.

Abstract translation: 尤其是通过将程序数据顺序地输入到耦合到至少四个平面的选定页面的页缓冲器以便对包括在所选页中的所选择的存储单元进行编程来操作半导体存储器件; 在四个平面中的每一个上执行程序操作; 在四个平面中的每一个上执行程序验证操作; 并且在确定所述四个平面中的至少两个平面中的所选择的页面已经通过了程序验证操作之后，在对所述页面缓冲器执行所述程序操作和所述程序验证操作的同时，将用于下一页的新程序数据输入到耦合到所述下一页的页缓冲器 剩下的两架飞机。

公开(公告)号：US20130121082A1

公开(公告)日：2013-05-16

申请号：US13726861

申请日：2012-12-26

Applicant: SK hynix Inc.

Inventor： Won Yeol CHOI ,  Eun Joung LEE

IPC: G11C16/34 ,  G11C16/06

CPC classification number: G11C16/3459 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/06 ,  G11C16/10 ,  G11C16/26 ,  G11C16/3436

Abstract: A method of operating a nonvolatile memory device includes determining whether a program operation is performed on even memory cells coupled to even bit lines of a selected page, setting a coupling resistance value between odd bit lines of the selected page and page buffers depending on whether the program operation for the even memory cells is performed, performing a program operation on the odd memory cells coupled to the odd bit lines, and coupling the odd bit line to the page buffer based on the set coupling resistance value and performing an verification operation for verifying whether threshold voltages of the odd memory cells on which the program operation is performed are a target voltage or more.

Abstract translation: 一种操作非易失性存储器件的方法包括确定是否对耦合到所选页面的偶数位线的偶数存储器单元执行编程操作，根据所选择的页面的奇数位线之间设置耦合电阻值， 执行对偶数存储单元的编程操作，对耦合到奇数位线的奇数存储单元执行编程操作，并且基于所设置的耦合电阻值将奇数位线耦合到页缓冲器，并执行用于验证的验证操作 是否执行编程操作的奇数存储单元的阈值电压是目标电压以上。