公开(公告)号：US20190088327A1

公开(公告)日：2019-03-21

申请号：US15914870

申请日：2018-03-07

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Yuichi ITO

IPC: G11C13/00 ,  G11C11/16 ,  H01L27/24 ,  H01L43/12 ,  H01L43/08

CPC classification number: G11C13/0069 ,  G11C11/161 ,  G11C11/1655 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  H01L27/228 ,  H01L27/2409 ,  H01L27/2454 ,  H01L27/2481 ,  H01L43/08 ,  H01L43/12

Abstract: A memory device includes first and second resistance change elements and first and second double-gate transistors. The first resistance change element includes first and second terminals. The second resistance change element includes a third terminal coupled to the first terminal and a fourth terminal. The first double-gate transistor includes a fifth terminal coupled to the second terminal, a sixth terminal, and a first gate coupled to a first word line and a second gate coupled to a second word line. The second double-gate transistor includes a seventh terminal coupled to the fourth terminal, an eighth element, and a third gate coupled to the first word line and a fourth gate coupled to a third word line.

公开(公告)号：US20190074045A1

公开(公告)日：2019-03-07

申请号：US15919876

申请日：2018-03-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SUK-SOO PYO ,  Hyun-Taek Jung ,  Tae-Joong Song

IPC: G11C11/16

CPC classification number: G11C11/1697 ,  G11C8/08 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/1693 ,  G11C11/5607 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0028 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0069 ,  G11C2013/0071 ,  G11C2213/79

Abstract: A resistive memory device includes: a voltage generator generating a write word line voltage according to activation of a write enable signal; a switch circuit outputting one of the write word line voltage and a read word line voltage in response to the write enable signal as an output voltage; a word line power path connected to the switch circuit to receive the output voltage; and a word line driver driving a word line according to a voltage applied to the word line power path, wherein a write command starts to be received after a certain delay following the activation of the write enable signal, and a write operation is performed within an activation period of the write enable signal in response to the received write command.

公开(公告)号：US20190074044A1

公开(公告)日：2019-03-07

申请号：US16081553

申请日：2017-03-01

Applicant: VIRGINIA COMMONWEALTH UNIVERSITY

Inventor： Jayasimha Atulasimha ,  Dhritiman Bhattcaharya ,  Md Mamun Al-Rashid

IPC: G11C11/16 ,  G11C11/56

CPC classification number: G11C11/1675 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/5607

Abstract: A fixed magnetic skyrmion in a memory or Boolean logic or non-Boolean computing element is reversibly switched or switchable (1) with only an electric field and without a magnetic field or spin current; and (2) using voltage control of magnetic anisotropy (VCMA) to reduce the spin current needed to switch the skyrmion. Some embodiments switch between four states: two skyrmion states and two ferromagnetic states. Other embodiments switch between two states which are both skyrmionic, in which case the switching process may use ferromagnetic intermediate states, or both ferromagnetic, in which case the switching process may use skyrmionic intermediate states, or between a Skyrmion and ferromagnetic state. Boolean and non-Boolean logic devices are also provided which are based on these switching methods.

公开(公告)号：US20180358070A1

公开(公告)日：2018-12-13

申请号：US15965830

申请日：2018-04-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： YOONJONG SONG ,  KILHO LEE ,  DAEEUN JEONG

IPC: G11C11/16 ,  H01L43/12 ,  H01L43/10 ,  H01L43/02

CPC classification number: G11C11/161 ,  G11C11/1659 ,  H01L43/02 ,  H01L43/10 ,  H01L43/12

Abstract: Disclosed are a magnetic memory device and a method of fabricating the same. The magnetic memory device comprises a bottom electrode on a substrate, a magnetic tunnel junction pattern including a first magnetic layer, a tunnel barrier layer, and a second magnetic layer that are sequentially stacked on the bottom electrode, and a top electrode on the magnetic tunnel junction pattern. The bottom electrode comprises a first bottom electrode and a second bottom electrode on the first bottom electrode. Each of the first and second bottom electrodes comprises metal nitride. The first bottom electrode has a crystallinity higher than that of the second bottom electrode.

公开(公告)号：US20180358069A1

公开(公告)日：2018-12-13

申请号：US15870486

申请日：2018-01-12

Applicant: SanDisk Technologies LLC

Inventor： Supraja SUNDARESAN ,  Sung-en WANG ,  Khin HTOO ,  Primit MODI

IPC: G11C11/16 ,  G11C13/00 ,  G11C5/14

CPC classification number: G11C11/161 ,  G11C5/147 ,  G11C8/08 ,  G11C11/1653 ,  G11C11/1655 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/1697 ,  G11C11/2253 ,  G11C11/2297 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/0038 ,  G11C13/0069 ,  G11C16/08 ,  G11C16/30 ,  G11C2213/71

Abstract: Disclosed is a device including a selected distributed driver, a first feedback control circuit, and a second feedback control circuit. The first feedback control circuit is coupled to the selected distributed driver. The first feedback control circuit is configured to maintain an output of the selected distributed driver within a first predetermined range. The second feedback control circuit is selectively coupled to the selected distributed driver and is configured to maintain the output of the selected distributed driver to be within a second predetermined range. The second predetermined range is within the first predetermined range.

公开(公告)号：US20180350419A1

公开(公告)日：2018-12-06

申请号：US15573904

申请日：2016-05-16

Applicant: TOHOKU UNIVERSITY

Inventor： Hiroki Koike ,  Tetsuo Endoh

IPC: G11C11/16

CPC classification number: G11C11/1697 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675

Abstract: A memory circuit (11) includes: a memory cell (MCij) including a variable-resistance element in which a resistance value varies substantially between two levels; a resistance-voltage conversion circuit that converts the resistance value of a memory cell (MCij) to be read into a data voltage; a reference circuit (RC1) including a series circuit of a variable-resistance element and a linear resistor, the variable-resistance element including substantially the same configuration as the configuration of the variable-resistance element included in the memory cell MCij and being set to a lower resistance of two levels; a reference voltage conversion circuit that converts the resistance value of the reference circuit (RCi) into a reference voltage; and a sense amplifier (SA) that determines data stored in the memory cell (MCij) by comparing the data voltage with the reference voltage.

公开(公告)号：US20180301199A1

公开(公告)日：2018-10-18

申请号：US15945119

申请日：2018-04-04

Applicant: TDK CORPORATION

Inventor： Tomoyuki SASAKI

IPC: G11C19/08 ,  H01L27/22 ,  H01L43/08 ,  H01L43/06 ,  G11C11/16 ,  H03K19/168

CPC classification number: G11C19/0841 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/5607 ,  G11C27/00 ,  H01F10/3254 ,  H01F10/329 ,  H01L27/226 ,  H01L43/06 ,  H01L43/08 ,  H01L43/10 ,  H03K19/168

Abstract: A magnetic domain wall type analog memory element includes: a magnetization fixed layer in which magnetization is oriented in a first direction; a non-magnetic layer provided in one surface of the magnetization fixed layer; a magnetic domain wall drive layer including a first area in which magnetization is oriented in the first direction, a second area in which magnetization is oriented in a second direction opposite to the first direction, and a magnetic domain wall formed as an interface between the areas and provided to sandwich the non-magnetic layer with respect to the magnetization fixed layer; and a current controller configured to cause a current to flow between the magnetization fixed layer and the second area at the time of reading.

公开(公告)号：US20180261269A1

公开(公告)日：2018-09-13

申请号：US14588819

申请日：2015-01-02

Applicant: Jannier Maximo Roiz Wilson

Inventor： Jannier Maximo Roiz Wilson

IPC: G11C11/16 ,  H01L27/22 ,  H01L43/02 ,  H01L43/10 ,  H01L43/12

CPC classification number: G11C11/161 ,  G11C11/1659 ,  H01L27/226 ,  H01L27/228 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12

Abstract: The present invention sets forth a new approach to Spin Transfer Torque MRAM that relies on 3D shape anisotropy and bulk-like ferromagnetic material properties in the free-layer to lower the write current and allow high TMR to a great extent independently of cell size and for any desired thermal stability of the cell.

公开(公告)号：US20180254076A1

公开(公告)日：2018-09-06

申请号：US15700769

申请日：2017-09-11

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Hirofumi MORISE ,  Tsuyoshi KONDO ,  Nobuyuki UMETSU ,  Yasuaki OOTERA ,  Susumu HASHIMOTO ,  Masaki KADO ,  Takuya SHIMADA ,  Michael Arnaud QUINSAT ,  Shiho NAKAMURA

IPC: G11C11/16 ,  H01L43/08

CPC classification number: G11C11/161 ,  G11C11/1655 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C19/0841 ,  H01L43/08

Abstract: According to an embodiment, a magnetic memory includes a first magnetic portion, a second magnetic portion, a first nonmagnetic portion, and a controller. The first magnetic portion includes a first portion and a second portion. The controller in a first operation supplies a first current from the first portion toward the second portion. The controller in a second operation supplies a second current to from the second portion toward the first portion. A first electrical resistance value can be different from a second electrical resistance value. The first electrical resistance value is between the second magnetic portion and the portion of the first magnetic portion before the first operation and the second operation are performed. The second electrical resistance value is between the second magnetic portion and the portion of the first magnetic portion after the first operation and the second operation are performed.

公开(公告)号：US20180233190A1

公开(公告)日：2018-08-16

申请号：US15695950

申请日：2017-09-05

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Shinya KOBAYASHI

IPC: G11C11/16

CPC classification number: G11C11/1675 ,  G11C11/161 ,  G11C11/1655 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1693 ,  G11C11/1695 ,  G11C11/1697 ,  H01L27/228 ,  H01L43/02 ,  H01L43/08

Abstract: A magnetic memory device includes a memory cell array, a counter circuit and a control circuit. The memory cell array includes a memory cell including a magneto resistive element in which writing is performed by current in a first direction or current in a second direction which is an opposite direction to the first direction. The memory cell array includes a first word line and a first bit line, both connected with the memory cell. The counter circuit counts the number of writing times in the first direction while the counter circuit is in electrical connection with the magneto resistive element. The control circuit performs writing in the second direction in the memory cell when the number of consecutive writing times in the first direction reaches a threshold number of times while the control circuit is in connection with the memory cell array.