公开(公告)号：US10367666B2

公开(公告)日：2019-07-30

申请号：US15471364

申请日：2017-03-28

Applicant: Xilinx, Inc.

Inventor： Hongtao Zhang ,  Yohan Frans ,  Geoffrey Zhang

IPC: H04B1/06 ,  H04L27/01 ,  H03M1/18 ,  H04L25/06 ,  H03M1/36

Abstract: A receiver includes: an automatic gain controller (AGC) configured to receive an analog signal; an analog-to-digital converter (ADC) configured to receive an output from the AGC and to output a digitized signal, wherein a most significant bit of the digitized signal corresponds to a sliced data, and a least significant bit of the digitized signal corresponds to an error signal; and an adaptation unit configured to control the AGC, the ADC, or both the AGC and the ADC, based at least in part on the digitized signal to achieve a desired data digitization and data slicing.

公开(公告)号：US09960902B1

公开(公告)日：2018-05-01

申请号：US15380653

申请日：2016-12-15

Applicant: Xilinx, Inc.

Inventor： Winson Lin ,  Yu Xu ,  Caleb S. Leung ,  Alan C. Wong ,  Christopher J. Borrelli ,  Yohan Frans ,  Kun-Yung Chang

IPC: H04L7/00 ,  H04L1/20

CPC classification number: H04L1/205 ,  H03L7/0814 ,  H04L7/0037 ,  H04L7/033 ,  H04L7/0337

Abstract: An example method of clock and data recovery in a receiver includes generating data samples and crossing samples of a received signal based on a data clock signal and a crossing clock signal, respectively, which are derived from a sampling clock signal; adjusting a phase of the sampling clock signal using a clock and data recovery (CDR) circuit based on the data samples and the crossing samples; adjusting relative phase between the data clock signal and the crossing clock signal from a first phase difference to a second phase difference that is less than ninety degrees; and reverting the relative phase between the data clock signal and the crossing clock signal to the first phase difference after a threshold time period.

公开(公告)号：US20180102797A1

公开(公告)日：2018-04-12

申请号：US15837791

申请日：2017-12-11

Applicant: Xilinx, Inc.

Inventor： Siok Wei Lim ,  Kok Lim Chan ,  Kee Hian Tan ,  Hongyuan Zhao ,  Chin Yang Koay ,  Yohan Frans ,  Kun-Yung Chang

IPC: H04B1/04 ,  H03M9/00 ,  H02M3/158 ,  H03K17/687

CPC classification number: H04B1/04 ,  H02M3/158 ,  H03K17/163 ,  H03K17/6872 ,  H03K19/0175 ,  H03M9/00

Abstract: A driver circuit includes a plurality of output circuits coupled in parallel between a differential input and a differential output and having a first common node and a second common node. Each of the plurality of output circuits includes a series combination of a pair of inverters and a pair of resistors, coupled between the differential input and the differential output; first source terminals of the pair of inverters coupled to the first common node; and second source terminals of the pair of inverters coupled to the second common node. The driver circuit further includes a first voltage regulator having an output coupled to the first common node of the plurality of output circuits; a second voltage regulator having an output coupled to the second common node of the plurality of circuits; and a current compensation circuit coupled between the outputs of the first voltage regulator and the second voltage regulator.

公开(公告)号：US09887710B1

公开(公告)日：2018-02-06

申请号：US15227853

申请日：2016-08-03

Applicant: Xilinx, Inc.

Inventor： Siok Wei Lim ,  Kok Lim Chan ,  Kee Hian Tan ,  Hongyuan Zhao ,  Chin Yang Koay ,  Yohan Frans ,  Kun-Yung Chang

IPC: H04B1/04 ,  H03K17/687 ,  H03M9/00 ,  H02M3/158

CPC classification number: H04B1/04 ,  H02M3/158 ,  H03K17/163 ,  H03K17/6872 ,  H03K19/0175 ,  H03M9/00

Abstract: A driver circuit includes a plurality of output circuits coupled in parallel between a differential input and a differential output and having a first common node and a second common node. Each of the plurality of output circuits includes a series combination of a pair of inverters and a pair of resistors, coupled between the differential input and the differential output; first source terminals of the pair of inverters coupled to the first common node; and second source terminals of the pair of inverters coupled to the second common node. The driver circuit further includes a first voltage regulator having an output coupled to the first common node of the plurality of output circuits; a second voltage regulator having an output coupled to the second common node of the plurality of circuits; and a current compensation circuit coupled between the outputs of the first voltage regulator and the second voltage regulator.

公开(公告)号：US09882703B1

公开(公告)日：2018-01-30

申请号：US15346434

申请日：2016-11-08

Applicant: Xilinx, Inc.

Inventor： Yu Xu ,  Winson Lin ,  Caleb S. Leung ,  Alan C. Wong ,  Christopher J. Borrelli ,  Yohan Frans ,  Kun-Yung Chang

IPC: H03D3/24 ,  H04L7/00 ,  H04L12/26 ,  H04L7/033

CPC classification number: H04L43/16 ,  H04L7/0025 ,  H04L7/0083 ,  H04L7/033 ,  H04L25/03 ,  H04L43/028

Abstract: An example method of clock and data recovery in a receiver includes generating data samples and crossing samples of a received signal based on a data phase and a crossing phase, respectively, of a sampling clock supplied by a phase interpolator in the receiver; generating a phase detect result signal in response to phase detection of the data samples and the crossing samples; filtering the phase detect result signal to generate a phase interpolator code, the phase interpolator generating the sampling clock based on the phase interpolator code; determining an average phase detect result from the phase detect result signal; and adjusting the phase interpolator code in response to the average phase detect result being less than a threshold value.

公开(公告)号：US09413524B1

公开(公告)日：2016-08-09

申请号：US14887744

申请日：2015-10-20

Applicant: Xilinx, Inc.

Inventor： Yu Xu ,  Yohan Frans ,  Kun-Yung Chang

IPC: H04L7/00 ,  H04L27/06 ,  H03L7/085 ,  H04B1/16

CPC classification number: H04L7/0087 ,  H04L7/0025 ,  H04L7/0337

Abstract: In an example, an apparatus for CDR includes at least one data register, at least one edge register having an input coupled to an output of the at least one data register, and a phase detector having inputs coupled to the output of the at least one data register and an output of the at least one edge register. The apparatus further includes a frequency accumulator coupled to an output of the phase detector, a dynamic gain circuit coupled to the output of the phase detector, and a phase accumulator and code generator circuit configured to generate codes to control a phase interpolator based on an output of the dynamic gain circuit and an output of the frequency accumulator.

Abstract translation: 在一个示例中，用于CDR的装置包括至少一个数据寄存器，至少一个边缘寄存器，其具有耦合到所述至少一个数据寄存器的输出的输入，以及相位检测器，其具有耦合到所述至少一个 数据寄存器和至少一个边沿寄存器的输出。 该装置还包括耦合到相位检测器的输出的频率累加器，耦合到相位检测器的输出的动态增益电路，以及相位累加器和代码发生器电路，被配置为基于输出来产生用于控制相位内插器的代码 的动态增益电路和频率累加器的输出。

公开(公告)号：US09379880B1

公开(公告)日：2016-06-28

申请号：US14795150

申请日：2015-07-09

Applicant: Xilinx, Inc.

Inventor： Yu Xu ,  Yohan Frans ,  Kun-Yung Chang

IPC: H04L7/02 ,  H04L7/00 ,  H04L7/04 ,  H04L7/10

CPC classification number: H04L7/0337

Abstract: Clock data recovery can be accomplished using a phase change determination circuit that generates, based upon detected phase differences between a capture clock signal and data signal, a delta signal and a delta selection signal. A calculation circuit generates a set of phase interpolation (PI) codes from prior and speculative values of the delta signal. A selection circuit selects, in response to the delta selection signal, between the sets of PI codes, which are provided as an output of the clock data recovery device.

Abstract translation: 时钟数据恢复可以使用相位变化确定电路来实现，相位变化确定电路基于检测到的捕获时钟信号和数据信号之间的相位差产生增量信号和增量选择信号。 计算电路从增量信号的先验值和推测值生成一组相位插值（PI）码。 选择电路响应于增量选择信号选择作为时钟数据恢复装置的输出提供的PI代码组。