公开(公告)号：US08841948B1

公开(公告)日：2014-09-23

申请号：US13830729

申请日：2013-03-14

Applicant: Xilinx, Inc.

Inventor： Jun-Chau Chien ,  Wayne Fang ,  Parag Upadhyaya ,  Jafar Savoj ,  Kun-Yung Chang

IPC: H03L7/06 ,  H03L7/07

CPC classification number: H03L7/081 ,  H03L7/087 ,  H03L7/0995 ,  H03L7/24

Abstract: An apparatus relates generally to an injection-controlled-locked phase-locked loop (“ICL-PLL”) is disclosed. In this apparatus, a delay-locked loop is coupled to an injection-locked phase-locked loop. An injection-locked oscillator of the injection-locked phase-locked loop is in a feedback loop path of the delay-locked loop.

Abstract translation: 一种装置一般涉及一种注射锁定锁相环（“ICL-PLL”）。 在该装置中，延迟锁定环耦合到注入锁定的锁相环。 注入锁相环的注入锁定振荡器处于延迟锁定环路的反馈回路中。

公开(公告)号：US08710883B1

公开(公告)日：2014-04-29

申请号：US13630192

申请日：2012-09-28

Applicant: Xilinx, Inc.

Inventor： Wayne Fang ,  Parag Upadhyaya

IPC: H03L7/06

CPC classification number: H03L7/0995 ,  H03L7/0891 ,  H03L7/093 ,  H03L2207/06

Abstract: An apparatus comprises a lock-loop circuit including an oscillator, a frequency detector, a charge pump, and a regulator. The regulator is coupled to provide a regulated signal to the oscillator to control frequency. The oscillator and the frequency detector are coupled to receive a reference clock signal. The reference clock signal is coupled to the oscillator to suppress noise in the oscillator by pulse injection. The frequency detector is coupled to receive an oscillator output from the oscillator.

Abstract translation: 一种装置包括一个包括振荡器，频率检测器，电荷泵和调节器的锁环电路。 调节器耦合以向振荡器提供调节信号以控制频率。 振荡器和频率检测器被耦合以接收参考时钟信号。 参考时钟信号耦合到振荡器，以通过脉冲注入来抑制振荡器中的噪声。 频率检测器被耦合以接收来自振荡器的振荡器输出。

公开(公告)号：US12072239B1

公开(公告)日：2024-08-27

申请号：US18128948

申请日：2023-03-30

Applicant: XILINX, INC.

Inventor： Zhaowen Wang ,  Mayank Raj ,  Chuan Xie ,  Sandeep Kumar ,  Muqseed Mohammad ,  Sukruth Pattanagiri Giriyappa ,  Stanley Y. Chen ,  Parag Upadhyaya ,  Yohan Frans

IPC: G01J1/44 ,  G01J1/02 ,  H03F3/45

CPC classification number: G01J1/44 ,  G01J1/0252 ,  H03F3/45076 ,  G01J2001/444 ,  G01J2001/446

Abstract: An integrated circuit (IC) device includes a controller circuitry having an input coupled to a photodiode of an optoelectronic circuitry and an output coupled to a heater of the optoelectronic circuitry, the controller circuitry configured to determine a center frequency of the optoelectronic circuitry based on a shape of an input signal received from the photodiode, and provide a heater signal to the heater based on the shape of the input signal and the center frequency of the optoelectronic circuitry.

公开(公告)号：US11695397B2

公开(公告)日：2023-07-04

申请号：US17398675

申请日：2021-08-10

Applicant: XILINX, INC.

Inventor： Wenfeng Zhang ,  Parag Upadhyaya

IPC: H03K5/003 ,  H03K3/037 ,  H04B1/16 ,  H04L27/32

CPC classification number: H03K5/003 ,  H03K3/037 ,  H04B1/16 ,  H04L27/32

Abstract: Receiver circuitry for a communication system includes signal processing circuitry, voltage digital-to-analog converter (DAC) circuitry, and slicer circuitry. The signal processing circuitry receives a data signal and generate a processed data signal. The voltage DAC circuitry generates a first threshold reference voltage. The slicer circuitry is coupled to an output of the signal processing circuitry. The slicer circuitry includes a capture flip-flop (CapFF) circuit that receives the processed data signal and the first threshold reference voltage. The CapFF circuit further generates a first data signal. The first CapFF circuit includes a first offset compensation circuit that adjusts a parasitic capacitance of the first CapFF circuit.

公开(公告)号：US11689207B1

公开(公告)日：2023-06-27

申请号：US17694550

申请日：2022-03-14

Applicant: XILINX, INC.

Inventor： Adebabay M. Bekele ,  Parag Upadhyaya

IPC: H03L7/099 ,  H03B5/12 ,  H03L7/093

CPC classification number: H03L7/099 ,  H03B5/1253 ,  H03B5/1296 ,  H03L7/093

Abstract: Phase-locked loop circuitry generates an output signal based on transformer based voltage controlled oscillator (VCO) circuitry. The VCO circuitry includes upper band circuitry including first oscillation circuitry, a first harmonic filter circuitry coupled to the first oscillation circuitry, and a first selection transistor coupled to the first harmonic filter circuitry and a current source. The first harmonic filter circuitry filters the output signal. The lower band circuitry includes second oscillation circuitry, a second harmonic filter circuitry coupled to the second oscillation circuitry, and a second selection transistor coupled to the second harmonic filter circuitry and the current source. The second harmonic filter circuitry filters the output signal.

公开(公告)号：US11190172B1

公开(公告)日：2021-11-30

申请号：US17031694

申请日：2020-09-24

Applicant: XILINX, INC.

Inventor： Mayank Raj ,  Parag Upadhyaya

IPC: H03K19/0185 ,  H04B17/18 ,  H04B10/516 ,  H03K3/356

Abstract: Examples described herein generally relate to integrated circuits that include a latch-based level shifter circuit with self-biasing. In an example, an integrated circuit includes first and second latches and an output stage circuit. Each of the first and second latches includes a bias circuit electrically connected to a respective latch node and configured to provide a bias voltage at the respective latch node, which is electrically coupled to a signal input node. The output stage circuit has first and second input nodes electrically connected to first and second output nodes of the first and second latches, respectively, and a third output node. The output stage circuit is configured to responsively pull up and pull down a voltage of the third output node in response to respective voltages of the first and second input nodes.

公开(公告)号：US10791009B1

公开(公告)日：2020-09-29

申请号：US16682806

申请日：2019-11-13

Applicant: Xilinx, Inc.

Inventor： Zhaoyin D. Wu ,  Parag Upadhyaya

IPC: H04L25/03 ,  H04L27/01 ,  H04L27/00 ,  H04L7/00

Abstract: Apparatus and associated methods relate to adapting a continuous time linear equalization circuit with minimum mean square error baud-rate clock and data recovery circuit to be able to lock to the center or near center of an eye diagram. In an illustrative example, a circuit may include an inter-symbol interference (ISI) detector configured to receive data and error samples, a summing circuit coupled to the output of the ISI detector, a moving average filter configured to receive the output of the summing circuit and generate an average output, a voter configured to generate a vote in response to the average output and a predetermined threshold, and, an accumulator and code generator configured to generate a code signal in response to the generated vote. By introducing the moving average filter and the voter, a quicker way to lock to the center or near center of an eye diagram may be obtained.

公开(公告)号：US20190229113A1

公开(公告)日：2019-07-25

申请号：US15875568

申请日：2018-01-19

Applicant: Xilinx, Inc.

Inventor： Zhaoyin D. Wu ,  Parag Upadhyaya ,  Kun-Yung Chang

IPC: H01L27/02 ,  H01L21/84 ,  H01L21/762 ,  H01L21/76 ,  H01L23/64 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L27/0288 ,  H01L21/7602 ,  H01L21/76297 ,  H01L21/76895 ,  H01L21/84 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/645

Abstract: Examples herein describe techniques for isolating portions of an IC that include sensitive components (e.g., inductors or capacitors) from return current in a grounding plane. An output current generated by a transmitter or driver in an IC can generate a magnetic field which induces return current in the grounding plane. If the return current is proximate the sensitive components, the return current can inject noise which can negatively impact other components in the IC. To isolate the sensitive components from the return current, embodiments herein include forming slots through the grounding structure which includes the grounding plane on one or more sides of the sensitive components.

公开(公告)号：US10270450B1

公开(公告)日：2019-04-23

申请号：US16110937

申请日：2018-08-23

Applicant: Xilinx, Inc.

Inventor： Shaojun Ma ,  Parag Upadhyaya ,  Didem Z. Turker Melek

IPC: H03K19/0185 ,  H03H11/28 ,  H03K19/0175 ,  H04B3/04 ,  H03K17/0812 ,  H03K19/018 ,  H04B1/04

Abstract: Methods and apparatus relate to a bidirectional differential interface having a voltage-mode transmit driver architecture formed of multiple selectively enabled slices for coarse output resistance impedance matching. In an illustrative example, the transmit driver may include a programmable resistance for fine-tuning to impedance match the output resistance for transmit operation. During receive operation, protective voltage may be proactively applied to gates of drive transistors, for example, to minimize voltage stresses applied by external signal sources. Some implementations may automatically float the sources of the drive transistors, for example, to prevent back-feeding externally driven signal currents during receive mode operations. The transmit driver may have programmable voltage swing on, for example, the upper and/or lower bounds to enhance compatibility. A programmable common mode voltage node may be selectively applied, for example, through common mode resistors for receive mode operations. Various embodiments may reduce pin count for high speed bidirectional I/O.

公开(公告)号：US10217703B2

公开(公告)日：2019-02-26

申请号：US15397612

申请日：2017-01-03

Applicant: Xilinx, Inc.

Inventor： Parag Upadhyaya ,  Jing Jing

IPC: H01L23/522 ,  H01L49/02 ,  H01L21/768 ,  H03B5/12 ,  H01L23/64 ,  H01L29/40

Abstract: An integrated circuit device is described. The integrated circuit device comprises a substrate; a plurality of metal routing interconnect layers; an inductor formed in at least one metal layer of the plurality of metal routing interconnect layers; and a bottom metal layer between the plurality of metal routing interconnect layers and the substrate; wherein a pattern ground shield is formed in the bottom metal layer. A method of implementing an integrated circuit device is also disclosed.