公开(公告)号：US20180041232A1

公开(公告)日：2018-02-08

申请号：US15227853

申请日：2016-08-03

Applicant: Xilinx, Inc.

Inventor： Siok Wei Lim ,  Kok Lim Chan ,  Kee Hian Tan ,  Hongyuan Zhao ,  Chin Yang Koay ,  Yohan Frans ,  Kun-Yung Chang

IPC: H04B1/04 ,  H03M9/00 ,  H02M3/158 ,  H03K17/687

CPC classification number: H04B1/04 ,  H02M3/158 ,  H03K17/163 ,  H03K17/6872 ,  H03K19/0175 ,  H03M9/00

Abstract: A driver circuit includes a plurality of output circuits coupled in parallel between a differential input and a differential output and having a first common node and a second common node. Each of the plurality of output circuits includes a series combination of a pair of inverters and a pair of resistors, coupled between the differential input and the differential output; first source terminals of the pair of inverters coupled to the first common node; and second source terminals of the pair of inverters coupled to the second common node. The driver circuit further includes a first voltage regulator having an output coupled to the first common node of the plurality of output circuits; a second voltage regulator having an output coupled to the second common node of the plurality of circuits; and a current compensation circuit coupled between the outputs of the first voltage regulator and the second voltage regulator.

公开(公告)号：US09654327B2

公开(公告)日：2017-05-16

申请号：US14723171

申请日：2015-05-27

Applicant: Xilinx, Inc.

Inventor： Yu Liao ,  Geoffrey Zhang ,  Hongtao Zhang ,  Kun-Yung Chang ,  Toan Pham ,  Zhaoyin D. Wu

IPC: H03K5/159 ,  H04L27/38 ,  H04L25/03

CPC classification number: H04L27/3809 ,  H04L25/03057 ,  H04L25/03885

Abstract: A receiver relates generally to channel adaptation. In this receiver, a first signal processing block is coupled to a communications channel. The first signal processing block includes: an AGC block and a CTLE block for receiving a modulated signal for providing an analog signal; an ADC for converting the analog signal to digital samples; and an FFE block for equalizing the digital samples to provide equalized samples. A second signal processing block includes: a DFE block for receiving the equalized sampled for providing re-equalized samples; and a slicer coupled to the DFE block for slicing the re-equalized samples. A receiver adaptation block is coupled to the first signal processing block and the second signal processing block. The receiver adaptation block is configured for providing an AGC adaptation, a CTLE adaptation, and a slicer adaptation to the communications channel.

公开(公告)号：US09379920B1

公开(公告)日：2016-06-28

申请号：US14707919

申请日：2015-05-08

Applicant: Xilinx, Inc.

Inventor： Yu Liao ,  Hongtao Zhang ,  Kun-Yung Chang ,  Geoffrey Zhang

IPC: H04L25/03 ,  H04L27/01

CPC classification number: H04L25/03057 ,  H04L25/03 ,  H04L25/03146 ,  H04L25/03878 ,  H04L25/03885 ,  H04L27/01 ,  H04L2025/0349 ,  H04L2025/03503

Abstract: In a receiver, a decision feedback equalizer (“DFE”) receives an analog input signal. The DFE includes a subtraction block for subtracting weighted postcursor decisions from an analog input signal to provide an analog output signal. A postcursor decision block coupled to the DFE compares the analog output signal against positive and negative values of a postcursor coefficient to provide first and second possible decisions for selecting a current postcursor-based decision therebetween responsive to a previous postcursor-based decision. A precursor cancellation block receives the analog output signal, the previous postcursor-based decision and the current postcursor-based decision for providing a digital output signal for a previous sample of the analog input signal.

Abstract translation: 在接收机中，判决反馈均衡器（“DFE”）接收模拟输入信号。 DFE包括用于从模拟输入信号减去加权后移判定的减法模块以提供模拟输出信号。 耦合到DFE的后端判定块将模拟输出信号与后移系数的正值和负值进行比较，以响应于先前的基于后期的判定来提供用于选择当前基于后台的判定的第一和第二可能决定。 前体消除块接收模拟输出信号，先前的基于后期的判定和当前的基于前后的判定，用于为模拟输入信号的先前样本提供数字输出信号。

公开(公告)号：US09379720B1

公开(公告)日：2016-06-28

申请号：US14715280

申请日：2015-05-18

Applicant: Xilinx, Inc.

Inventor： Yu Xu ,  Santiago G. Asuncion ,  Tianqi Tang ,  Toan Pham ,  Kun-Yung Chang

IPC: H03D3/24 ,  H03L7/087 ,  H04L7/04

CPC classification number: H04L7/0337

Abstract: Clock data recovery can be accomplished using a phase path circuit that is configured to receive a data signal and a clock signal. A phase detection circuit detects phase differences between the data signal and a plurality of clock signals and generates a phase adjustment signal based upon a majority voting of the detected phase differences. Speculative calculation circuits generate speculative phase selection signals. Selection circuits select, in response to the phase adjustment signal, from speculative phase selection signals to provide outputs of the phase path circuit.

Abstract translation: 可以使用被配置为接收数据信号和时钟信号的相位路径电路来实现时钟数据恢复。 相位检测电路检测数据信号和多个时钟信号之间的相位差，并且基于检测到的相位差的多数投票产生相位调整信号。 投机计算电路产生推测相位选择信号。 选择电路响应于相位调整信号从推测相位选择信号中选择以提供相位路径电路的输出。

公开(公告)号：US09313017B1

公开(公告)日：2016-04-12

申请号：US14737330

申请日：2015-06-11

Applicant: Xilinx, Inc.

Inventor： Yu Liao ,  Geoffrey Zhang ,  Hongtao Zhang ,  Zhaoyin D. Wu ,  Kun-Yung Chang

IPC: H04L7/00 ,  H04L7/033

CPC classification number: H04L7/0087 ,  H04L7/0025 ,  H04L7/0062 ,  H04L25/03

Abstract: In an example, a clock data recovery (CDR) circuit for a receiver includes a timing error detector circuit, a loop filter, and a phase interpolator. The timing error detector circuit is coupled to receive, at a baud-rate, data samples and error samples for symbols received by the receiver. The timing error detector circuit is operable to generate both a timing error value and an estimated waveform value per symbol based on the data samples and the error samples. The loop filter is coupled to the timing error detector to receive timing error values. The phase interpolator is coupled to the loop filter to receive filtered timing error values, the phase interpolator operable to generate a control signal to adjust a sampling phase used to generate the data samples and the error samples.

Abstract translation: 在一个示例中，用于接收机的时钟数据恢复（CDR）电路包括定时误差检测器电路，环路滤波器和相位内插器。 定时误差检测器电路被耦合以以波特率接收由接收器接收的符号的数据样本和误差样本。 定时误差检测器电路可操作以基于数据样本和误差样本同时产生每个符号的定时误差值和估计波形值。 环路滤波器耦合到定时误差检测器以接收定时误差值。 相位内插器耦合到环路滤波器以接收滤波的定时误差值，相位插值器可操作以产生控制信号以调整用于生成数据样本和误差采样的采样相位。

公开(公告)号：US09209960B1

公开(公告)日：2015-12-08

申请号：US14550576

申请日：2014-11-21

Applicant: Xilinx, Inc.

Inventor： Caleb S. Leung ,  Alan C. Wong ,  Christopher J. Borrelli ,  Yu Xu ,  Yohan Frans ,  Kun-Yung Chang

IPC: H04L7/00

CPC classification number: H04L7/0337 ,  H04L7/0025

Abstract: A method relates generally to a receiver. In such a method, a check of a clock and data recovery block of the receiver for a metastable state is performed. A phase input to a phase interpolator of the receiver is changed to cause the clock and data recovery block of the receiver to exit the metastable state within a time limit. To check for the metastable state, a phase difference in received data is determined, and the phase difference is determined to be less than a threshold for the clock and data recovery block being in the metastable state.

Abstract translation: 一种方法一般涉及接收机。 在这种方法中，执行用于亚稳态的接收机的时钟和数据恢复块的检查。 接收机的相位内插器的相位输入被改变，以使接收器的时钟和数据恢复块在时间限制内退出亚稳态。 为了检查亚稳态，确定接收数据中的相位差，并且确定相位差小于时钟和数据恢复块处于亚稳态的阈值。