公开(公告)号：US10340357B2

公开(公告)日：2019-07-02

申请号：US15964572

申请日：2018-04-27

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Yi-Huan Chen ,  Chien-Chih Chou ,  Ta-Wei Lin ,  Fu-Jier Fan ,  Kong-Beng Thei ,  Yi-Sheng Chen ,  Szu-Hsien Liu

IPC分类号： H01L29/49 ,  H01L29/06 ,  H01L29/40 ,  H01L27/088 ,  H01L21/8234

摘要： In some embodiments, an integrated circuit is provided. The integrated circuit may include an inner ring-shaped isolation structure that is disposed in a semiconductor substrate. Further, the inner-ring shaped isolation structure may demarcate a device region. An inner ring-shaped well is disposed in the semiconductor substrate and surrounds the inner ring-shaped isolation structure. A plurality of dummy gates are arranged over the inner ring-shaped well. Moreover, the plurality of dummy gates are arranged within an interlayer dielectric layer.

公开(公告)号：US10164037B2

公开(公告)日：2018-12-25

申请号：US15475294

申请日：2017-03-31

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Ker-Hsiao Huo ,  Kong-Beng Thei ,  Chih-Wen Albert Yao ,  Fu-Jier Fan ,  Chen-Liang Chu ,  Ta-Yuan Kung ,  Yi-Huan Chen ,  Yu-Bin Zhao ,  Ming-Ta Lei ,  Li-Hsuan Yeh

IPC分类号： H01L29/423 ,  H01L21/28 ,  H01L29/40 ,  H01L29/06 ,  H01L29/08

摘要： A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate having a top surface, a source region, and a drain region. The semiconductor device structure includes a gate structure over the top surface and extending into the semiconductor substrate. The gate structure in the semiconductor substrate is between the source region and the drain region and separates the source region from the drain region. The semiconductor device structure includes an isolation structure in the semiconductor substrate and surrounding the source region, the drain region, and the gate structure in the semiconductor substrate.

公开(公告)号：US10050033B1

公开(公告)日：2018-08-14

申请号：US15703116

申请日：2017-09-13

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Kong-Beng Thei ,  Chien-Chih Chou ,  Fu-Jier Fan ,  Hsiao-Chin Tuan ,  Yi-Huan Chen ,  Alexander Kalnitsky ,  Yi-Sheng Chen

IPC分类号： H01L27/088 ,  H01L27/02 ,  H01L27/04 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/51

摘要： The present disclosure relates to an integrated circuit (IC) and a method of formation. In some embodiments, a first oxide component is disposed on a substrate within a medium voltage region. A first high-k dielectric component is disposed on the substrate within a low voltage region and a second high-k dielectric component disposed on the first oxide component within the medium voltage region. A first gate electrode separates from the substrate by the first high-k dielectric component. A second gate electrode separates from the substrate by the first oxide component and the second high-k dielectric component.

公开(公告)号：US11276684B2

公开(公告)日：2022-03-15

申请号：US16579661

申请日：2019-09-23

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Yi-Huan Chen ,  Chien-Chih Chou ,  Alexander Kalnitsky ,  Kong-Beng Thei

IPC分类号： H01L27/088 ,  H01L27/06 ,  H01L29/66 ,  H01L29/78 ,  H01L49/02 ,  H01L21/8234 ,  H01L23/522 ,  H01L21/762

摘要： Some embodiments relate to an integrated circuit (IC) that includes a semiconductor substrate. A shallow trench isolation region downwardly extends into the frontside of the semiconductor substrate and is filled with dielectric material. A first capacitor plate and a second capacitor plate are disposed in the shallow trench isolation region. The first capacitor plate and the second capacitor plate have first and second sidewall structures, respectively, that are substantially parallel to one another and that are separated from one another by the dielectric material of the shallow trench isolation region.

公开(公告)号：US20210193813A1

公开(公告)日：2021-06-24

申请号：US17192280

申请日：2021-03-04

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Yi-Huan Chen ,  Chien-Chih Chou ,  Ta-Wei Lin ,  Fu-Jier Fan ,  Kong-Beng Thei ,  Yi-Sheng Chen ,  Szu-Hsien Liu

IPC分类号： H01L29/49 ,  H01L21/76 ,  H01L21/768 ,  H01L21/762 ,  H01L27/088 ,  H01L29/06 ,  H01L29/40 ,  H01L21/8234

摘要： In some embodiments, an integrated circuit is provided. The integrated circuit may include an inner ring-shaped isolation structure that is disposed in a semiconductor substrate. Further, the inner-ring shaped isolation structure may demarcate a device region. An inner ring-shaped well is disposed in the semiconductor substrate and surrounds the inner ring-shaped isolation structure. A plurality of dummy gates are arranged over the inner ring-shaped well. Moreover, the plurality of dummy gates are arranged within an interlayer dielectric layer.

公开(公告)号：US10991693B2

公开(公告)日：2021-04-27

申请号：US16732450

申请日：2020-01-02

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Yi-Huan Chen ,  Chien-Chih Chou ,  Kong-Beng Thei

IPC分类号： H01L27/092 ,  H01L29/10 ,  H01L29/66 ,  H01L21/8238 ,  H01L21/84 ,  H01L29/06 ,  H01L29/423

摘要： The present disclosure relates to an integrated circuit (IC) that includes a boundary region defined between a low voltage region, and a method of formation. In some embodiments, the integrated circuit comprises a first gate boundary dielectric layer disposed over a substrate in the low voltage region. A second gate boundary dielectric layer is disposed over the substrate in the high voltage region having a thickness greater than that of the first boundary dielectric layer. The first boundary dielectric layer meets the second boundary dielectric layer at the boundary region. A first polysilicon component is disposed within the boundary region over the first boundary dielectric layer and the second gate boundary layer. A second polysilicon component is disposed within the boundary region over the first polysilicon component. A hard mask component is disposed over the first polysilicon component and laterally neighbored to the second polysilicon component.

公开(公告)号：US20200381420A1

公开(公告)日：2020-12-03

申请号：US16579661

申请日：2019-09-23

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Yi-Huan Chen ,  Chien-Chih Chou ,  Alexander Kalnitsky ,  Kong-Beng Thei

IPC分类号： H01L27/06 ,  H01L29/66 ,  H01L29/78 ,  H01L27/088 ,  H01L21/762 ,  H01L21/8234 ,  H01L23/522 ,  H01L49/02

摘要： Some embodiments relate to an integrated circuit (IC) that includes a semiconductor substrate. A shallow trench isolation region downwardly extends into the frontside of the semiconductor substrate and is filled with dielectric material. A first capacitor plate and a second capacitor plate are disposed in the shallow trench isolation region. The first capacitor plate and the second capacitor plate have first and second sidewall structures, respectively, that are substantially parallel to one another and that are separated from one another by the dielectric material of the shallow trench isolation region.

公开(公告)号：US10804093B2

公开(公告)日：2020-10-13

申请号：US16587819

申请日：2019-09-30

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Yi-Huan Chen ,  Chien-Chih Chou ,  Kong-Beng Thei ,  Meng-Han Lin

IPC分类号： H01L21/02 ,  H01L23/00 ,  H01L29/735 ,  H01L21/3105 ,  H01L29/66 ,  H01L29/08 ,  H01L29/06 ,  H01L29/10

摘要： In some embodiments, a bipolar junction transistor (BJT) is provided. The BJT may include a collector region that is disposed within a semiconductor substrate. A base region that is disposed within the semiconductor substrate and arranged within the collector region. An emitter region that is disposed within the semiconductor substrate and arranged within the base region. A pre-metal dielectric layer that is disposed over an upper surface of the semiconductor substrate and that separates the upper surface of the semiconductor substrate from a lowermost metal interconnect layer. A first plurality of dishing prevention columns that are arranged over the emitter region and within the pre-metal dielectric layer, where the plurality of dishing prevention columns each include a dummy gate that is conductive and electrically floating.

公开(公告)号：US20200091310A1

公开(公告)日：2020-03-19

申请号：US16693670

申请日：2019-11-25

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Kong-Beng Thei ,  Chien-Chih Chou ,  Hsiao-Chin Tuan ,  Yi-Huan Chen ,  Alexander Kalnitsky

IPC分类号： H01L29/66 ,  H01L21/768 ,  H01L29/78

摘要： In some embodiments, a semiconductor device is provided. The semiconductor device includes a pair of source/drain regions disposed in a semiconductor substrate, where the source/drain regions are laterally spaced. A gate electrode is disposed over the semiconductor substrate between the source/drain regions. Sidewall spacers are disposed over the semiconductor substrate on opposite sides of the gate electrode. A silicide blocking structure is disposed over the sidewalls spacers, where respective sides of the source/drain regions facing the gate electrode are spaced apart from outer sides of the sidewall spacers and are substantially aligned with outer sidewalls of the silicide blocking structure.

公开(公告)号：US20200083343A1

公开(公告)日：2020-03-12

申请号：US16683530

申请日：2019-11-14

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Yi-Huan Chen ,  Chien-Chih Chou ,  Ta-Wei Lin ,  Fu-Jier Fan ,  Kong-Beng Thei ,  Yi-Sheng Chen ,  Szu-Hsien Liu

IPC分类号： H01L29/49 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/40 ,  H01L29/06 ,  H01L21/762 ,  H01L21/76

摘要： In some embodiments, an integrated circuit is provided. The integrated circuit may include an inner ring-shaped isolation structure that is disposed in a semiconductor substrate. Further, the inner-ring shaped isolation structure may demarcate a device region. An inner ring-shaped well is disposed in the semiconductor substrate and surrounds the inner ring-shaped isolation structure. A plurality of dummy gates are arranged over the inner ring-shaped well. Moreover, the plurality of dummy gates are arranged within an interlayer dielectric layer.