公开(公告)号：US11569363B2

公开(公告)日：2023-01-31

申请号：US17192280

申请日：2021-03-04

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Yi-Huan Chen ,  Chien-Chih Chou ,  Ta-Wei Lin ,  Fu-Jier Fan ,  Kong-Beng Thei ,  Yi-Sheng Chen ,  Szu-Hsien Liu

IPC分类号： H01L29/49 ,  H01L29/06 ,  H01L29/40 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/76 ,  H01L21/762 ,  H01L21/768

摘要： In some embodiments, an integrated circuit is provided. The integrated circuit may include an inner ring-shaped isolation structure that is disposed in a semiconductor substrate. Further, the inner-ring shaped isolation structure may demarcate a device region. An inner ring-shaped well is disposed in the semiconductor substrate and surrounds the inner ring-shaped isolation structure. A plurality of dummy gates are arranged over the inner ring-shaped well. Moreover, the plurality of dummy gates are arranged within an interlayer dielectric layer.

公开(公告)号：US20190097013A1

公开(公告)日：2019-03-28

申请号：US15964572

申请日：2018-04-27

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Yi-Huan Chen ,  Chien-Chih Chou ,  Ta-Wei Lin ,  Fu-Jier Fan ,  Kong-Beng Thei ,  Yi-Sheng Chen ,  Szu-Hsien Liu

IPC分类号： H01L29/49 ,  H01L29/06 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/40

CPC分类号： H01L29/4916 ,  H01L21/76 ,  H01L21/76229 ,  H01L21/823437 ,  H01L21/823481 ,  H01L27/088 ,  H01L29/0603 ,  H01L29/401

摘要： In some embodiments, an integrated circuit is provided. The integrated circuit may include an inner ring-shaped isolation structure that is disposed in a semiconductor substrate. Further, the inner-ring shaped isolation structure may demarcate a device region. An inner ring-shaped well is disposed in the semiconductor substrate and surrounds the inner ring-shaped isolation structure. A plurality of dummy gates are arranged over the inner ring-shaped well. Moreover, the plurality of dummy gates are arranged within an interlayer dielectric layer.

公开(公告)号：US11469307B2

公开(公告)日：2022-10-11

申请号：US17098867

申请日：2020-11-16

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Yi-Huan Chen ,  Kong-Beng Thei ,  Chien-Chih Chou ,  Alexander Kalnitsky ,  Szu-Hsien Liu ,  Huan-Chih Yuan

IPC分类号： H01L29/423 ,  H01L29/40 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/78

摘要： In some embodiments, the present disclosure relates to a semiconductor device that includes a well region with a substrate. A source region and a drain region are arranged within the substrate on opposite sides of the well region. A gate electrode is arranged over the well region, has a bottom surface arranged below a topmost surface of the substrate, and extends between the source and drain regions. A trench isolation structure surrounds the source region, the drain region, and the gate electrode. A gate dielectric structure separates the gate electrode from the well region, the source, region, the drain region, and the trench isolation structure. The gate electrode structure has a central portion and a corner portion. The central portion has a first thickness, and the corner portion has a second thickness that is greater than the first thickness.

公开(公告)号：US20220102518A1

公开(公告)日：2022-03-31

申请号：US17098867

申请日：2020-11-16

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Yi-Huan Chen ,  Kong-Beng Thei ,  Chien-Chih Chou ,  Alexander Kalnitsky ,  Szu-Hsien Liu ,  Huan-Chih Yuan

IPC分类号： H01L29/423 ,  H01L21/762 ,  H01L29/40

摘要： In some embodiments, the present disclosure relates to a semiconductor device that includes a well region with a substrate. A source region and a drain region are arranged within the substrate on opposite sides of the well region. A gate electrode is arranged over the well region, has a bottom surface arranged below a topmost surface of the substrate, and extends between the source and drain regions. A trench isolation structure surrounds the source region, the drain region, and the gate electrode. A gate dielectric structure separates the gate electrode from the well region, the source, region, the drain region, and the trench isolation structure. The gate electrode structure has a central portion and a corner portion. The central portion has a first thickness, and the corner portion has a second thickness that is greater than the first thickness.

公开(公告)号：US10516029B2

公开(公告)日：2019-12-24

申请号：US16437137

申请日：2019-06-11

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Yi-Huan Chen ,  Chien-Chih Chou ,  Ta-Wei Lin ,  Fu-Jier Fan ,  Kong-Beng Thei ,  Yi-Sheng Chen ,  Szu-Hsien Liu

IPC分类号： H01L29/49 ,  H01L29/06 ,  H01L29/40 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/76 ,  H01L21/762

摘要： In some embodiments, an integrated circuit is provided. The integrated circuit may include an inner ring-shaped isolation structure that is disposed in a semiconductor substrate. Further, the inner-ring shaped isolation structure may demarcate a device region. An inner ring-shaped well is disposed in the semiconductor substrate and surrounds the inner ring-shaped isolation structure. A plurality of dummy gates are arranged over the inner ring-shaped well. Moreover, the plurality of dummy gates are arranged within an interlayer dielectric layer.

公开(公告)号：US20210193813A1

公开(公告)日：2021-06-24

申请号：US17192280

申请日：2021-03-04

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Yi-Huan Chen ,  Chien-Chih Chou ,  Ta-Wei Lin ,  Fu-Jier Fan ,  Kong-Beng Thei ,  Yi-Sheng Chen ,  Szu-Hsien Liu

IPC分类号： H01L29/49 ,  H01L21/76 ,  H01L21/768 ,  H01L21/762 ,  H01L27/088 ,  H01L29/06 ,  H01L29/40 ,  H01L21/8234

摘要： In some embodiments, an integrated circuit is provided. The integrated circuit may include an inner ring-shaped isolation structure that is disposed in a semiconductor substrate. Further, the inner-ring shaped isolation structure may demarcate a device region. An inner ring-shaped well is disposed in the semiconductor substrate and surrounds the inner ring-shaped isolation structure. A plurality of dummy gates are arranged over the inner ring-shaped well. Moreover, the plurality of dummy gates are arranged within an interlayer dielectric layer.

公开(公告)号：US20200083343A1

公开(公告)日：2020-03-12

申请号：US16683530

申请日：2019-11-14

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Yi-Huan Chen ,  Chien-Chih Chou ,  Ta-Wei Lin ,  Fu-Jier Fan ,  Kong-Beng Thei ,  Yi-Sheng Chen ,  Szu-Hsien Liu

IPC分类号： H01L29/49 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/40 ,  H01L29/06 ,  H01L21/762 ,  H01L21/76

摘要： In some embodiments, an integrated circuit is provided. The integrated circuit may include an inner ring-shaped isolation structure that is disposed in a semiconductor substrate. Further, the inner-ring shaped isolation structure may demarcate a device region. An inner ring-shaped well is disposed in the semiconductor substrate and surrounds the inner ring-shaped isolation structure. A plurality of dummy gates are arranged over the inner ring-shaped well. Moreover, the plurality of dummy gates are arranged within an interlayer dielectric layer.

公开(公告)号：US20190296121A1

公开(公告)日：2019-09-26

申请号：US16437137

申请日：2019-06-11

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Yi-Huan Chen ,  Chien-Chih Chou ,  Ta-Wei Lin ,  Fu-Jier Fan ,  Kong-Beng Thei ,  Yi-Sheng Chen ,  Szu-Hsien Liu

IPC分类号： H01L29/49 ,  H01L29/06 ,  H01L21/76 ,  H01L21/762 ,  H01L29/40

摘要： In some embodiments, an integrated circuit is provided. The integrated circuit may include an inner ring-shaped isolation structure that is disposed in a semiconductor substrate. Further, the inner-ring shaped isolation structure may demarcate a device region. An inner ring-shaped well is disposed in the semiconductor substrate and surrounds the inner ring-shaped isolation structure. A plurality of dummy gates are arranged over the inner ring-shaped well. Moreover, the plurality of dummy gates are arranged within an interlayer dielectric layer.

公开(公告)号：US09853149B1

公开(公告)日：2017-12-26

申请号：US15283722

申请日：2016-10-03

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chao-Hsuing Chen ,  Fu-Jier Fan ,  Yi-Huan Chen ,  Kong-Beng Thei ,  Ker-Hsiao Huo ,  Szu-Hsien Liu

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119 ,  H01L29/78 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66 ,  H01L29/06 ,  H01L21/306

CPC分类号： H01L21/30604 ,  H01L21/31053 ,  H01L29/0653 ,  H01L29/1054 ,  H01L29/42368 ,  H01L29/4916 ,  H01L29/7833 ,  Y02E10/50

摘要： The present disclosure relates an integrated circuit (IC) and a method for manufacturing same. A polysilicon layer is formed over a first region of a substrate and has a plurality of polysilicon structures that are packed with respect to one another to define a first packing density. A dummy layer is formed over a second region of the substrate and has a plurality of dummy structures that are packed with respect to one another to define a second packing density, where the first packing density and second packing density are substantially similar. An inter-layer dielectric layer is formed over the first region and second region of the substrate. Dishing of at least the second region of the substrate concurrent with a chemical-mechanical polish is generally inhibited by the first packing density and second packing density after forming the inter-layer dielectric layer.

公开(公告)号：US20210280577A1

公开(公告)日：2021-09-09

申请号：US17316155

申请日：2021-05-10

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Yi-Huan Chen ,  Kong-Beng Thei ,  Fu-Jier Fan ,  Ker-Hsiao Huo ,  Kau-Chu Lin ,  Li-Hsuan Yeh ,  Szu-Hsien Liu ,  Yi-Sheng Chen

IPC分类号： H01L27/088 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/423 ,  H01L27/092

摘要： A method includes forming an isolation region extending into a semiconductor substrate, etching a top portion of the isolation region to form a recess in the isolation region, and forming a gate stack extending into the recess and overlapping a lower portion of the isolation region. A source region and a drain region are formed on opposite sides of the gate stack. The gate stack, the source region, and the drain region are parts of a Metal-Oxide-Semiconductor (MOS) device.